Searched refs:GPIO (Results 1 – 17 of 17) sorted by relevance
/trusted-firmware-a/include/dt-bindings/pinctrl/ |
A D | stm32-pinfunc.h | 11 #define GPIO 0x0 macro
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/trusted-firmware-a/include/drivers/nxp/gpio/ |
A D | nxp_gpio.h | 38 #error Please define GPIO register endianness
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/trusted-firmware-a/include/plat/marvell/armada/a8k/common/ |
A D | armada_common.h | 32 GPIO, enumerator
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/trusted-firmware-a/plat/marvell/armada/a8k/a70x0_amc/board/ |
A D | marvell_plat_config.c | 135 .detection_method = GPIO,
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/trusted-firmware-a/plat/marvell/armada/a8k/a70x0/board/ |
A D | marvell_plat_config.c | 138 .detection_method = GPIO,
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/trusted-firmware-a/plat/marvell/armada/a8k/a80x0/board/ |
A D | marvell_plat_config.c | 189 .detection_method = GPIO,
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/ |
A D | porting.rst.txt | 52 - GPIO 68 implemented using GPIO: mpp 33 (SW5). 76 Press reset and keep pressing the button connected to the chosen GPIO pin. A
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/trusted-firmware-a/docs/plat/marvell/armada/ |
A D | porting.rst | 52 - GPIO 68 implemented using GPIO: mpp 33 (SW5). 76 Press reset and keep pressing the button connected to the chosen GPIO pin. A
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/trusted-firmware-a/plat/nxp/soc-lx2160a/ |
A D | soc.def | 57 # Defining the endianness for NXP GPIO
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/trusted-firmware-a/docs/plat/nxp/ |
A D | nxp-ls-fuse-prov.rst | 11 | | Platform | Jumper | Switch | LED to Verify | Through GPIO Pin (=number) | 203 Note: If GPIO Pin supports enabling POVDD, it can be done through the below input_fuse_file.
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/nxp/ |
A D | nxp-ls-fuse-prov.rst.txt | 11 | | Platform | Jumper | Switch | LED to Verify | Through GPIO Pin (=number) | 203 Note: If GPIO Pin supports enabling POVDD, it can be done through the below input_fuse_file.
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/trusted-firmware-a/plat/marvell/armada/a8k/common/ |
A D | plat_ble_setup.c | 696 case GPIO: in ble_skip_current_image()
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
A D | change-log.md.txt | 1034 - GPIO, NCDI, SPMC drivers 1046 - following drivers: SD, EMMC, QSPI, FLEXSPI, GPIO, GIC, CSU, PMU, DDR 2100 - rpi3: Include GPIO driver in all BL stages and use same "clock-less" setup 2227 - rpi3: gpio: Simplify GPIO setup 2296 - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC code
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/trusted-firmware-a/docs/ |
A D | change-log.md | 1034 - GPIO, NCDI, SPMC drivers 1046 - following drivers: SD, EMMC, QSPI, FLEXSPI, GPIO, GIC, CSU, PMU, DDR 2100 - rpi3: Include GPIO driver in all BL stages and use same "clock-less" setup 2227 - rpi3: gpio: Simplify GPIO setup 2296 - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC code
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/trusted-firmware-a/docs/getting_started/ |
A D | porting-guide.rst | 527 If the platform port uses the PL061 GPIO driver, the following constant may 532 much memory is allocated for PL061 GPIO controllers. The default value is
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
A D | porting-guide.rst.txt | 527 If the platform port uses the PL061 GPIO driver, the following constant may 532 much memory is allocated for PL061 GPIO controllers. The default value is
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/trusted-firmware-a/docs/build/latex/ |
A D | trustedfirmware-a.tex | 6100 If the platform port uses the PL061 GPIO driver, the following constant may 6107 much memory is allocated for PL061 GPIO controllers. The default value is 37220 GPIO 37256 implemented using GPIO: mpp 33 (SW5). 37269 Press reset and keep pressing the button connected to the chosen GPIO pin. A 39146 Through GPIO Pin (=number) 54349 GPIO, NCDI, SPMC drivers 54401 following drivers: SD, EMMC, QSPI, FLEXSPI, GPIO, GIC, CSU, PMU, DDR 58663 rpi3: Include GPIO driver in all BL stages and use same “clock\sphinxhyphen{}less” setup 59044 rpi3: gpio: Simplify GPIO setup [all …]
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