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Searched refs:IMR1_CORE0_M4 (Results 1 – 8 of 8) sorted by relevance

/trusted-firmware-a/plat/imx/imx8m/imx8mm/
A Dgpc.c33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mn/
A Dgpc.c35 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/include/
A Dgpc_reg.h22 #define IMR1_CORE0_M4 0x50 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mn/include/
A Dgpc_reg.h22 #define IMR1_CORE0_M4 0x50 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mm/include/
A Dgpc_reg.h22 #define IMR1_CORE0_M4 0x50 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mp/include/
A Dgpc_reg.h22 #define IMR1_CORE0_M4 0x58 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dgpc.c136 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mp/
A Dgpc.c314 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()

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