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Searched refs:IMR1_CORE3_A53 (Results 1 – 9 of 9) sorted by relevance

/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dgpc.c135 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
145 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mm/
A Dgpc.c32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mn/
A Dgpc.c34 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/include/
A Dgpc_reg.h21 #define IMR1_CORE3_A53 0x1D0 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mn/include/
A Dgpc_reg.h21 #define IMR1_CORE3_A53 0x1D0 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mm/include/
A Dgpc_reg.h21 #define IMR1_CORE3_A53 0x1D0 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mp/include/
A Dgpc_reg.h21 #define IMR1_CORE3_A53 0x1A8 macro
/trusted-firmware-a/plat/imx/imx8m/
A Dgpc_common.c19 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53
/trusted-firmware-a/plat/imx/imx8m/imx8mp/
A Dgpc.c313 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()

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