Searched refs:IMX_GPC_BASE (Results 1 – 9 of 9) sorted by relevance
| /trusted-firmware-a/plat/imx/imx8m/imx8mq/ |
| A D | gpc.c | 82 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
85 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
91 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
96 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
109 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_set_cluster_powerdown()
112 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_set_cluster_powerdown()
118 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
122 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
148 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
152 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
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| /trusted-firmware-a/plat/imx/imx8m/ |
| A D | gpc_common.c | 115 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
121 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
132 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
134 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
150 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
158 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
164 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown()
225 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_set_sys_lpm()
233 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_set_sys_lpm()
244 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | in imx_set_rbc_count()
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| /trusted-firmware-a/plat/imx/imx8m/imx8mm/ |
| A D | gpc.c | 29 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
30 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
36 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
41 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
61 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81); in imx_gpc_init()
62 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init()
66 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init()
70 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
79 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init()
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| /trusted-firmware-a/plat/imx/imx8m/imx8mn/ |
| A D | gpc.c | 31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
35 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
38 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
43 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
63 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); in imx_gpc_init()
64 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init()
68 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init()
72 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
81 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init()
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| /trusted-firmware-a/plat/imx/imx8m/imx8mp/ |
| A D | gpc.c | 199 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
310 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
311 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
314 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
317 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
322 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
342 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); in imx_gpc_init()
343 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init()
347 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init()
351 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
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| /trusted-firmware-a/plat/imx/imx8m/imx8mq/include/ |
| A D | platform_def.h | 65 #define IMX_GPC_BASE U(0x303a0000) macro
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| /trusted-firmware-a/plat/imx/imx8m/imx8mm/include/ |
| A D | platform_def.h | 94 #define IMX_GPC_BASE U(0x303a0000) macro
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| /trusted-firmware-a/plat/imx/imx8m/imx8mn/include/ |
| A D | platform_def.h | 79 #define IMX_GPC_BASE U(0x303a0000) macro
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| /trusted-firmware-a/plat/imx/imx8m/imx8mp/include/ |
| A D | platform_def.h | 97 #define IMX_GPC_BASE U(0x303a0000) macro
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