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Searched refs:IMX_SRC_BASE (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a/plat/imx/imx8m/
A Dgpc_common.c35 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), in imx_set_cpu_secure_entry()
37 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, in imx_set_cpu_secure_entry()
65 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
/trusted-firmware-a/plat/imx/imx8m/imx8mm/
A Dgpc.c86 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
87 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/trusted-firmware-a/plat/imx/common/
A Dimx_sip_handler.c161 mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET, in imx_src_handler()
164 mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET, in imx_src_handler()
169 val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET); in imx_src_handler()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dgpc.c176 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
177 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mp/
A Dgpc.c210 while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8))) in imx_gpc_pm_domain_enable()
368 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
369 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mn/
A Dgpc.c88 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/include/
A Dplatform_def.h64 #define IMX_SRC_BASE U(0x30390000) macro
/trusted-firmware-a/plat/imx/imx8m/imx8mm/include/
A Dplatform_def.h93 #define IMX_SRC_BASE U(0x30390000) macro
/trusted-firmware-a/plat/imx/imx8m/imx8mn/include/
A Dplatform_def.h78 #define IMX_SRC_BASE U(0x30390000) macro
/trusted-firmware-a/plat/imx/imx8m/imx8mp/include/
A Dplatform_def.h96 #define IMX_SRC_BASE U(0x30390000) macro

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