1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef PM_API_IOCTL_H 12 #define PM_API_IOCTL_H 13 14 #include "pm_common.h" 15 16 //ioctl id 17 enum { 18 IOCTL_GET_RPU_OPER_MODE = 0, 19 IOCTL_SET_RPU_OPER_MODE = 1, 20 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 21 IOCTL_TCM_COMB_CONFIG = 3, 22 IOCTL_SET_TAPDELAY_BYPASS = 4, 23 IOCTL_SET_SGMII_MODE = 5, 24 IOCTL_SD_DLL_RESET = 6, 25 IOCTL_SET_SD_TAPDELAY = 7, 26 /* Ioctl for clock driver */ 27 IOCTL_SET_PLL_FRAC_MODE = 8, 28 IOCTL_GET_PLL_FRAC_MODE = 9, 29 IOCTL_SET_PLL_FRAC_DATA = 10, 30 IOCTL_GET_PLL_FRAC_DATA = 11, 31 IOCTL_WRITE_GGS = 12, 32 IOCTL_READ_GGS = 13, 33 IOCTL_WRITE_PGGS = 14, 34 IOCTL_READ_PGGS = 15, 35 /* IOCTL for ULPI reset */ 36 IOCTL_ULPI_RESET = 16, 37 /* Set healthy bit value */ 38 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 39 IOCTL_AFI = 18, 40 /* Probe counter read/write */ 41 IOCTL_PROBE_COUNTER_READ = 19, 42 IOCTL_PROBE_COUNTER_WRITE = 20, 43 IOCTL_OSPI_MUX_SELECT = 21, 44 /* IOCTL for USB power request */ 45 IOCTL_USB_SET_STATE = 22, 46 /* IOCTL to get last reset reason */ 47 IOCTL_GET_LAST_RESET_REASON = 23, 48 /* AI engine NPI ISR clear */ 49 IOCTL_AIE_ISR_CLEAR = 24, 50 /* Register SGI to ATF */ 51 IOCTL_REGISTER_SGI = 25, 52 /* Runtime feature configuration */ 53 IOCTL_SET_FEATURE_CONFIG = 26, 54 IOCTL_GET_FEATURE_CONFIG = 27, 55 }; 56 57 //RPU operation mode 58 #define PM_RPU_MODE_LOCKSTEP 0U 59 #define PM_RPU_MODE_SPLIT 1U 60 61 //RPU boot mem 62 #define PM_RPU_BOOTMEM_LOVEC 0U 63 #define PM_RPU_BOOTMEM_HIVEC 1U 64 65 //RPU tcm mpde 66 #define PM_RPU_TCM_SPLIT 0U 67 #define PM_RPU_TCM_COMB 1U 68 69 //tap delay signal type 70 #define PM_TAPDELAY_NAND_DQS_IN 0U 71 #define PM_TAPDELAY_NAND_DQS_OUT 1U 72 #define PM_TAPDELAY_QSPI 2U 73 #define PM_TAPDELAY_MAX 3U 74 75 //tap delay bypass 76 #define PM_TAPDELAY_BYPASS_DISABLE 0U 77 #define PM_TAPDELAY_BYPASS_ENABLE 1U 78 79 //sgmii mode 80 #define PM_SGMII_DISABLE 0U 81 #define PM_SGMII_ENABLE 1U 82 83 enum tap_delay_type { 84 PM_TAPDELAY_INPUT, 85 PM_TAPDELAY_OUTPUT, 86 }; 87 88 //dll reset type 89 #define PM_DLL_RESET_ASSERT 0U 90 #define PM_DLL_RESET_RELEASE 1U 91 #define PM_DLL_RESET_PULSE 2U 92 93 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 94 unsigned int ioctl_id, 95 unsigned int arg1, 96 unsigned int arg2, 97 unsigned int *value); 98 #endif /* PM_API_IOCTL_H */ 99