1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SSPM_REG_H__ 8 #define __SSPM_REG_H__ 9 10 #include "platform_def.h" 11 12 #define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100) 13 #define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8) 14 #define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC) 15 #define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204) 16 17 #define STANDBYWFI_EN(n) (1 << (n + 8)) 18 #define GIC_IRQOUT_EN(n) (1 << (n + 0)) 19 20 #define NF_MCDI_MBOX 19 21 #define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0 22 #define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1 23 #define MCDI_MBOX_BUCK_POWER_OFF_MASK 2 24 #define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3 25 #define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4 26 #define MCDI_MBOX_BOOTADDR 5 27 #define MCDI_MBOX_PAUSE_ACTION 6 28 #define MCDI_MBOX_AVAIL_CPU_MASK 7 29 #define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8 30 #define MCDI_MBOX_ACTION_STAT 9 31 #define MCDI_MBOX_CLUSTER_0_CNT 10 32 #define MCDI_MBOX_CLUSTER_1_CNT 11 33 #define MCDI_MBOX_CPU_ISOLATION_MASK 12 34 #define MCDI_MBOX_PAUSE_ACK 13 35 #define MCDI_MBOX_PENDING_ON_EVENT 14 36 #define MCDI_MBOX_PROF_CMD 15 37 #define MCDI_MBOX_DRCC_CALI_DONE 16 38 #define MCDI_MBOX_HP_CMD 17 39 #define MCDI_MBOX_HP_ACK 18 40 41 #endif /* __SSPM_REG_H__ */ 42