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Searched refs:MC_SECURITY_CFG0_0 (Results 1 – 7 of 7) sorted by relevance

/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_memctrl.c73 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); in plat_memctrl_tzdram_setup()
A Dplat_trampoline.S138 mov x3, #MC_SECURITY_CFG0_0
/trusted-firmware-a/plat/nvidia/tegra/drivers/memctrl/
A Dmemctrl_v1.c92 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); in tegra_memctrl_tzdram_setup()
/trusted-firmware-a/plat/nvidia/tegra/include/t210/
A Dtegra_def.h240 #define MC_SECURITY_CFG0_0 U(0x70) macro
/trusted-firmware-a/plat/nvidia/tegra/include/t186/
A Dtegra_def.h159 #define MC_SECURITY_CFG0_0 U(0x70) macro
/trusted-firmware-a/plat/nvidia/tegra/include/t194/
A Dtegra_def.h96 #define MC_SECURITY_CFG0_0 U(0x70) macro
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_memctrl.c674 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); in plat_memctrl_tzdram_setup()
689 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK; in plat_memctrl_tzdram_setup()

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