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Searched refs:MIDR_IMPL_MASK (Results 1 – 13 of 13) sorted by relevance

/trusted-firmware-a/lib/cpus/aarch64/
A Dcpuamu.c25 midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | in midr_match()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_sip_calls.c130 impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in plat_sip_handler()
A Dplat_psci_handlers.c378 impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_on_finish()
438 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
A Dplat_setup.c204 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in plat_early_platform_setup()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dmce.c118 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in mce_get_curr_cpu_ari_base()
139 MIDR_IMPL_MASK; in mce_get_curr_cpu_ops()
A Dnvg.c207 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in nvg_online_core()
A Dari.c330 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in ari_online_core()
/trusted-firmware-a/include/lib/cpus/aarch32/
A Dcpu_macros.S16 #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
/trusted-firmware-a/plat/nvidia/tegra/common/
A Dtegra_bl31_setup.c189 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) in bl31_early_platform_setup2()
/trusted-firmware-a/include/lib/cpus/aarch64/
A Dcpu_macros.S13 #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_psci_handlers.c468 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
/trusted-firmware-a/include/arch/aarch32/
A Darch.h15 #define MIDR_IMPL_MASK U(0xff) macro
/trusted-firmware-a/include/arch/aarch64/
A Darch.h16 #define MIDR_IMPL_MASK U(0xff) macro

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