Searched refs:MIDR_PN_SHIFT (Results 1 – 12 of 12) sorted by relevance
| /trusted-firmware-a/include/lib/cpus/aarch32/ |
| A D | cpu_macros.S | 17 (MIDR_PN_MASK << MIDR_PN_SHIFT)
224 ubfx r0, r0, #MIDR_PN_SHIFT, #12
225 ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
| /trusted-firmware-a/plat/imx/common/ |
| A D | imx8_helpers.S | 33 ubfx x0, x0, MIDR_PN_SHIFT, #12
34 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
| /trusted-firmware-a/include/lib/cpus/aarch64/ |
| A D | cpu_macros.S | 14 (MIDR_PN_MASK << MIDR_PN_SHIFT)
301 ubfx x0, x0, MIDR_PN_SHIFT, #12
302 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
| /trusted-firmware-a/plat/rockchip/common/aarch64/ |
| A D | plat_helpers.S | 36 ubfx x0, x0, MIDR_PN_SHIFT, #12
37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
| /trusted-firmware-a/lib/cpus/aarch64/ |
| A D | cpuamu.c | 26 (MIDR_PN_MASK << MIDR_PN_SHIFT); in midr_match()
|
| /trusted-firmware-a/plat/renesas/common/include/ |
| A D | rcar_def.h | 276 #define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
277 #define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
|
| /trusted-firmware-a/plat/renesas/common/aarch64/ |
| A D | plat_helpers.S | 352 ubfx x1, x0, MIDR_PN_SHIFT, #12
353 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
| /trusted-firmware-a/plat/nvidia/tegra/common/aarch64/ |
| A D | tegra_helpers.S | 65 mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
67 lsr x0, x0, #MIDR_PN_SHIFT
|
| /trusted-firmware-a/plat/renesas/rzg/ |
| A D | bl2_plat_setup.c | 711 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
|
| /trusted-firmware-a/include/arch/aarch32/ |
| A D | arch.h | 22 #define MIDR_PN_SHIFT U(4) macro
|
| /trusted-firmware-a/plat/renesas/rcar/ |
| A D | bl2_plat_setup.c | 851 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
|
| /trusted-firmware-a/include/arch/aarch64/ |
| A D | arch.h | 25 #define MIDR_PN_SHIFT U(0x4) macro
|
Completed in 22 milliseconds