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Searched refs:MISC1_CFG_BASE (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a/plat/mediatek/mt8195/drivers/dfd/
A Dplat_dfd.h30 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro
31 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
33 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
35 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
42 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
44 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
45 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
46 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
48 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
49 #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
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A Dplat_dfd.c141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.h23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) macro
24 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
26 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
28 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
29 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
34 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
36 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
37 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
38 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
40 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
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A Dplat_dfd.c124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a/plat/mediatek/mt8183/include/
A Dplat_debug.h14 #define MISC1_CFG_BASE 0xb00 macro
16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)

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