| /trusted-firmware-a/plat/mediatek/mt6795/ |
| A D | plat_topology.c | 15 if (aff_lvl > MPIDR_AFFLVL1) in plat_get_aff_count()
18 if (aff_lvl == MPIDR_AFFLVL1) in plat_get_aff_count()
|
| A D | plat_pm.c | 340 if (afflvl >= MPIDR_AFFLVL1) { in plat_affinst_suspend()
370 if (afflvl >= MPIDR_AFFLVL1) { in plat_affinst_on_finish()
404 if (afflvl >= MPIDR_AFFLVL1) { in plat_affinst_suspend_finish()
|
| /trusted-firmware-a/plat/imx/common/ |
| A D | imx8_psci.c | 45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
|
| /trusted-firmware-a/plat/rockchip/common/ |
| A D | plat_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
231 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
267 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
288 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
332 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
|
| /trusted-firmware-a/plat/nvidia/tegra/soc/t210/ |
| A D | plat_psci_handlers.c | 65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state()
112 if (lvl == MPIDR_AFFLVL1) in tegra_soc_get_target_pwr_state()
117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { in tegra_soc_get_target_pwr_state()
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; in tegra_soc_pwr_domain_suspend()
507 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in tegra_soc_pwr_domain_on_finish()
|
| /trusted-firmware-a/plat/imx/imx8m/include/ |
| A D | imx8m_psci.h | 11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
|
| /trusted-firmware-a/plat/amlogic/g12a/include/ |
| A D | platform_def.h | 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/amlogic/gxl/include/ |
| A D | platform_def.h | 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/marvell/armada/a8k/common/mss/ |
| A D | mss_pm_ipc.c | 45 MPIDR_AFFLVL1]); in mss_pm_ipc_msg_send()
|
| /trusted-firmware-a/plat/amlogic/gxbb/include/ |
| A D | platform_def.h | 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/layerscape/board/ls1043/include/ |
| A D | ls_def.h | 31 #define LS_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/imx/imx8qm/include/ |
| A D | platform_def.h | 27 #define IMX_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/brcm/board/stingray/src/ |
| A D | pm.c | 66 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in brcm_pwr_domain_on_finish()
|
| /trusted-firmware-a/plat/qti/sc7180/inc/ |
| A D | platform_def.h | 32 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/qti/sc7280/inc/ |
| A D | platform_def.h | 32 #define QTI_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/rpi/rpi4/include/ |
| A D | platform_def.h | 29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/imx/imx8qx/ |
| A D | imx8qx_psci.c | 127 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend()
203 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend_finish()
|
| /trusted-firmware-a/include/plat/marvell/armada/a3k/common/ |
| A D | marvell_def.h | 36 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/marvell/armada/a8k/common/include/ |
| A D | platform_def.h | 178 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/imx/imx7/picopi/include/ |
| A D | platform_def.h | 26 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/mediatek/mt8183/ |
| A D | plat_pm.c | 332 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_off()
351 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_on_finish()
367 bool afflvl1 = (pds[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF); in plat_mtk_power_domain_suspend()
|
| /trusted-firmware-a/plat/imx/imx7/warp7/include/ |
| A D | platform_def.h | 28 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/include/plat/marvell/armada/a8k/common/ |
| A D | marvell_def.h | 33 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/marvell/armada/a3k/common/include/ |
| A D | platform_def.h | 169 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
| /trusted-firmware-a/plat/hisilicon/poplar/include/ |
| A D | platform_def.h | 133 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
|