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Searched refs:MSS_SRAM_PM_CONTROL_BASE (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a/plat/marvell/armada/common/mss/
A Dmss_mem.h12 #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000) macro
A Dmss_scp_bootloader.c182 mss_pm_crtl = (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; in mss_ap_load_image()
192 VERBOSE("MSS Control Block = 0x%x\n", MSS_SRAM_PM_CONTROL_BASE); in mss_ap_load_image()
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_bl31_setup.c61 (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; in marvell_bl31_mss_init()

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