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Searched refs:MVEBU_AP0 (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a/include/drivers/marvell/
A Dcache_llc.h25 #define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
26 #define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
27 #define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
A Dccu.h37 #define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
/trusted-firmware-a/drivers/marvell/mochi/
A Dap807_setup.c25 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \
29 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \
268 cp110_temp_base = MVEBU_AP_IO_BASE(MVEBU_AP0); in update_cp110_default_win()
296 init_io_win(MVEBU_AP0); in ap_init()
299 init_ccu(MVEBU_AP0); in ap_init()
A Dapn806_setup.c23 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
27 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
262 init_io_win(MVEBU_AP0); in ap_init()
265 init_ccu(MVEBU_AP0); in ap_init()
/trusted-firmware-a/plat/marvell/armada/a8k/common/mss/
A Dmss_bl2_setup.c69 if (ccu_is_win_enabled(MVEBU_AP0, win_id)) in bl2_plat_mmap_init()
73 ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id); in bl2_plat_mmap_init()
84 init_io_win(MVEBU_AP0); in bl2_plat_mmap_init()
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_ble_setup.c177 ccu_restore_win_all(MVEBU_AP0); in ble_plat_mmap_config()
179 iow_restore_win_all(MVEBU_AP0); in ble_plat_mmap_config()
184 ccu_save_win_all(MVEBU_AP0); in ble_plat_mmap_config()
186 iow_save_win_all(MVEBU_AP0); in ble_plat_mmap_config()
188 init_ccu(MVEBU_AP0); in ble_plat_mmap_config()
190 init_io_win(MVEBU_AP0); in ble_plat_mmap_config()
A Dplat_bl31_setup.c99 tz_enable_win(MVEBU_AP0, tz_map, win_id); in marvell_bl31_security_setup()
/trusted-firmware-a/plat/marvell/armada/a8k/common/aarch64/
A Dplat_arch_config.c14 #define CCU_HTC_ASET (MVEBU_CCU_BASE(MVEBU_AP0) + 0x264)
/trusted-firmware-a/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h14 #define MVEBU_AP0 0x0 macro
/trusted-firmware-a/drivers/marvell/
A Dccu.c63 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \

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