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Searched refs:MVEBU_CP_REGS_BASE (Results 1 – 13 of 13) sorted by relevance

/trusted-firmware-a/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h33 #define MVEBU_CP_REGS_BASE(cp_index) (MVEBU_AP_IO_BASE(0) + \ macro
50 #define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
52 #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
55 (MVEBU_CP_REGS_BASE(cp_index) + \
58 (MVEBU_CP_REGS_BASE(cp_index) + \
60 #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \
66 #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000)
85 #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000)
86 #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000)
87 #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000)
/trusted-firmware-a/plat/marvell/octeontx/otx2/t91/t9130/board/
A Dmarvell_plat_config.c30 case MVEBU_CP_REGS_BASE(0): in marvell_get_amb_memory_map()
34 case MVEBU_CP_REGS_BASE(1): in marvell_get_amb_memory_map()
35 case MVEBU_CP_REGS_BASE(2): in marvell_get_amb_memory_map()
131 case MVEBU_CP_REGS_BASE(0): in marvell_get_iob_memory_map()
135 case MVEBU_CP_REGS_BASE(1): in marvell_get_iob_memory_map()
139 case MVEBU_CP_REGS_BASE(2): in marvell_get_iob_memory_map()
/trusted-firmware-a/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/
A Dmarvell_plat_config.c36 case MVEBU_CP_REGS_BASE(0): in marvell_get_amb_memory_map()
40 case MVEBU_CP_REGS_BASE(1): in marvell_get_amb_memory_map()
44 case MVEBU_CP_REGS_BASE(2): in marvell_get_amb_memory_map()
162 case MVEBU_CP_REGS_BASE(0): in marvell_get_iob_memory_map()
166 case MVEBU_CP_REGS_BASE(1): in marvell_get_iob_memory_map()
170 case MVEBU_CP_REGS_BASE(2): in marvell_get_iob_memory_map()
/trusted-firmware-a/plat/marvell/armada/a8k/common/mss/
A Dmss_bl2_setup.c34 {MVEBU_CP_REGS_BASE(0), 0x4000000, IO_0_TID}
88 cp110_amb_init(MVEBU_CP_REGS_BASE(cp)); in bl2_plat_mmap_init()
124 return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_REGS_OFFSET; in bl2_plat_get_cp_mss_regs()
129 return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_SRAM_OFFSET; in bl2_plat_get_cp_mss_sram()
139 uint32_t revision = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); in bl2_plat_get_cp_count()
A Dmss_bl31_setup.c21 uintptr_t sram = MVEBU_CP_REGS_BASE(cp) + MSS_CP_SRAM_OFFSET; in mss_start_cp_cm3()
22 uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET; in mss_start_cp_cm3()
/trusted-firmware-a/plat/marvell/armada/a8k/a80x0_mcbin/board/
A Dmarvell_plat_config.c140 case MVEBU_CP_REGS_BASE(0): in marvell_get_iob_memory_map()
144 case MVEBU_CP_REGS_BASE(1): in marvell_get_iob_memory_map()
/trusted-firmware-a/plat/marvell/armada/a8k/a80x0_puzzle/board/
A Dmarvell_plat_config.c144 case MVEBU_CP_REGS_BASE(0): in marvell_get_iob_memory_map()
148 case MVEBU_CP_REGS_BASE(1): in marvell_get_iob_memory_map()
/trusted-firmware-a/plat/marvell/armada/a8k/a80x0/board/
A Dmarvell_plat_config.c110 case MVEBU_CP_REGS_BASE(0): in marvell_get_iob_memory_map()
114 case MVEBU_CP_REGS_BASE(1): in marvell_get_iob_memory_map()
/trusted-firmware-a/drivers/marvell/mg_conf_cm3/
A Dmg_conf_cm3.c15 #define MG_CM3_CONFI_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000)
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_bl31_setup.c124 cp110_init(MVEBU_CP_REGS_BASE(cp), in bl31_plat_arch_setup()
A Dplat_ble_setup.c213 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); in ble_plat_avs_config()
446 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); in ble_plat_svc_config()
734 cp110_ble_init(MVEBU_CP_REGS_BASE(0)); in ble_plat_setup()
/trusted-firmware-a/plat/marvell/armada/common/
A Dmrvl_sip_svc.c66 if (*addr == MVEBU_CP_REGS_BASE(cp_nr)) in is_cp_range_valid()
/trusted-firmware-a/drivers/marvell/mochi/
A Dap807_setup.c279 cp110_base = MVEBU_CP_REGS_BASE(cp_id); in update_cp110_default_win()

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