Home
last modified time | relevance | path

Searched refs:MVEBU_REGS_BASE (Results 1 – 19 of 19) sorted by relevance

/trusted-firmware-a/plat/marvell/armada/a3k/common/include/
A Da3700_plat_def.h25 #define MVEBU_REGS_BASE 0xD0000000 macro
32 #define DEVICE0_BASE MVEBU_REGS_BASE
57 #define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000)
58 #define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000)
69 #define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00)
83 #define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE)
95 #define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000)
107 #define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200)
119 #define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500)
126 #define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
[all …]
A Dplatform_def.h121 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
122 #define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE)
123 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
166 #define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
/trusted-firmware-a/drivers/marvell/secure_dfx_access/
A Dmisc_dfx.c22 #define SAR_BASE (MVEBU_REGS_BASE + 0x6F8200)
24 #define AP_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8240)
25 #define JTAG_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8244)
26 #define EFUSE_CTRL (MVEBU_REGS_BASE + 0x6F8008)
27 #define EFUSE_LD_BASE (MVEBU_REGS_BASE + 0x6F8F00)
29 #define EFUSE_HD_BASE (MVEBU_REGS_BASE + 0x6F9000)
33 #define AP806_CA72MP2_0_PLL_CR_0_BASE (MVEBU_REGS_BASE + 0x6F8278)
34 #define AP806_CA72MP2_0_PLL_CR_1_BASE (MVEBU_REGS_BASE + 0x6F8280)
35 #define AP806_CA72MP2_0_PLL_CR_2_BASE (MVEBU_REGS_BASE + 0x6F8284)
36 #define AP806_CA72MP2_0_PLL_SR_BASE (MVEBU_REGS_BASE + 0x6F8C94)
[all …]
/trusted-firmware-a/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h28 #define MVEBU_REGS_BASE 0xF0000000 macro
30 #define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE
35 #define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000)
41 #define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300)
43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000)
46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000)
47 #define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000)
48 #define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000)
49 #define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000)
65 #define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000)
[all …]
A Dplatform_def.h131 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
132 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
171 #define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000)
/trusted-firmware-a/plat/marvell/armada/a8k/common/mss/
A Dmss_pm_ipc.c25 #define MSS_SISR (MVEBU_REGS_BASE + 0x5800D0)
26 #define MSS_SISTR (MVEBU_REGS_BASE + 0x5800D8)
A Dmss_bl2_setup.c134 return MVEBU_REGS_BASE + MSS_AP_REGS_OFFSET; in bl2_plat_get_ap_mss_regs()
/trusted-firmware-a/plat/marvell/armada/a8k/common/aarch64/
A Dplat_arch_config.c16 #define MVEBU_SF_REG (MVEBU_REGS_BASE + 0x40)
18 #define MVEBU_DFX_REG(cluster_id) (MVEBU_REGS_BASE + 0x6F82A0 + \
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_pm.c29 #define MVEBU_CCU_RVBAR(cpu) (MVEBU_REGS_BASE + 0x640 + (cpu * 4))
30 #define MVEBU_CCU_CPU_UN_RESET(cpu) (MVEBU_REGS_BASE + 0x650 + (cpu * 4))
77 (MVEBU_REGS_BASE + 0x6F8230)
91 (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))
101 (MVEBU_REGS_BASE + 0x1A50 + \
109 (MVEBU_REGS_BASE + 0x680000 + 0x100)
326 mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4); in plat_marvell_cpu_on()
A Dplat_bl31_setup.c75 mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); in marvell_bl31_mss_init()
/trusted-firmware-a/drivers/marvell/mochi/
A Dapn806_setup.c58 #define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000)
66 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
70 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
A Dap807_setup.c71 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
75 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
/trusted-firmware-a/plat/marvell/armada/a3k/common/
A Dio_addr_dec.c14 #define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \
16 #define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \
18 #define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \
A Da3700_sip_svc.c67 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); in mrvl_sip_smc_handler()
A Ddram_win.c269 if (mvebu_get_dram_size(MVEBU_REGS_BASE) <= _2GB_) in cpu_wins_init()
A Dplat_pm.c38 #define MVEBU_CPU_1_RESET_VECTOR (MVEBU_REGS_BASE + 0x14044)
39 #define MVEBU_CPU_1_RESET_REG (MVEBU_REGS_BASE + 0xD00C)
/trusted-firmware-a/plat/marvell/armada/common/mss/
A Dmss_mem.h12 #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000)
/trusted-firmware-a/plat/marvell/armada/common/
A Dmrvl_sip_svc.c132 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); in mrvl_sip_smc_handler()
/trusted-firmware-a/drivers/marvell/comphy/
A Dphy-comphy-3700.c27 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178)
30 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)

Completed in 20 milliseconds