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Searched refs:MVEBU_RFU_BASE (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h35 #define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000) macro
36 #define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE)
62 #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2))
63 #define MVEBU_AP_GPIO_REGS (MVEBU_RFU_BASE + 0x5040)
67 #define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
78 #define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \
/trusted-firmware-a/drivers/marvell/mochi/
A Dap807_setup.c33 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
38 #define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \
42 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
65 #define DSS_SCR_REG (MVEBU_RFU_BASE + 0x208)
77 #define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
A Dapn806_setup.c31 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
35 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
72 #define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
/trusted-firmware-a/drivers/marvell/
A Dap807_clocks_init.c16 (MVEBU_RFU_BASE + 0x82A8 + (0xA58 * (cluster)))
37 (MVEBU_RFU_BASE + 0x82E0 + (0x8 * (cluster)))
/trusted-firmware-a/include/drivers/marvell/mochi/
A Dcp110_setup.h34 #define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730)
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_pm.c824 mmio_write_32(MVEBU_RFU_BASE + MVEBU_RFU_GLOBL_SW_RST, 0x0); in plat_marvell_system_reset()

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