1 /*
2  * Copyright (c) 2019, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NCORE_CCU_H
8 #define NCORE_CCU_H
9 
10 
11 #define NCORE_CCU_OFFSET		0xf7000000
12 
13 
14 /* Coherent Sub-System Address Map */
15 #define NCORE_CAIU_OFFSET		0x00000
16 #define NCORE_CAIU_SIZE			0x01000
17 
18 #define NCORE_NCBU_OFFSET		0x60000
19 #define NCORE_NCBU_SIZE			0x01000
20 
21 #define NCORE_DIRU_OFFSET		0x80000
22 #define NCORE_DIRU_SIZE			0x01000
23 
24 #define NCORE_CMIU_OFFSET		0xc0000
25 #define NCORE_CMIU_SIZE			0x01000
26 
27 #define NCORE_CSR_OFFSET		0xff000
28 #define NCORE_CSADSERO			0x00040
29 #define NCORE_CSUIDR			0x00ff8
30 #define NCORE_CSIDR			0x00ffc
31 
32 /* Directory Unit Register Map */
33 #define NCORE_DIRUSFER			0x00010
34 #define NCORE_DIRUMRHER			0x00070
35 #define NCORE_DIRUSFMCR			0x00080
36 #define NCORE_DIRUSFMAR			0x00084
37 
38 /* Coherent Agent Interface Unit Register Map */
39 #define NCORE_CAIUIDR			0x00ffc
40 
41 /* Snoop Enable Register */
42 #define NCORE_DIRUCASER0		0x00040
43 #define NCORE_DIRUCASER1		0x00044
44 #define NCORE_DIRUCASER2		0x00048
45 #define NCORE_DIRUCASER3		0x0004c
46 
47 #define NCORE_CSADSER0			0x00040
48 #define NCORE_CSADSER1			0x00044
49 #define NCORE_CSADSER2			0x00048
50 #define NCORE_CSADSER3			0x0004c
51 
52 /* Protocols Definition */
53 #define ACE_W_DVM			0
54 #define ACE_L_W_DVM			1
55 #define ACE_WO_DVM			2
56 #define ACE_L_WO_DVM			3
57 
58 /* Bypass OC Ram Firewall */
59 #define NCORE_FW_OCRAM_BLK_BASE		0x100200
60 #define NCORE_FW_OCRAM_BLK_CGF1		0x04
61 #define NCORE_FW_OCRAM_BLK_CGF2		0x08
62 #define NCORE_FW_OCRAM_BLK_CGF3		0x0c
63 #define NCORE_FW_OCRAM_BLK_CGF4		0x10
64 
65 #define OCRAM_PRIVILEGED_MASK		BIT(29)
66 #define OCRAM_SECURE_MASK		BIT(30)
67 
68 /* Macros */
69 #define NCORE_CCU_REG(base)		(NCORE_CCU_OFFSET + (base))
70 #define NCORE_CCU_CSR(reg)		(NCORE_CCU_REG(NCORE_CSR_OFFSET)\
71 						+ (reg))
72 #define NCORE_CCU_DIR(reg)		(NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
73 						+ (reg))
74 #define NCORE_CCU_CAI(reg)		(NCORE_CCU_REG(NCORE_CAIU_OFFSET)\
75 						+ (reg))
76 
77 #define DIRECTORY_UNIT(x, reg)		(NCORE_CCU_DIR(reg)\
78 						+ NCORE_DIRU_SIZE * (x))
79 #define COH_AGENT_UNIT(x, reg)		(NCORE_CCU_CAI(reg)\
80 						+ NCORE_CAIU_SIZE * (x))
81 
82 #define COH_CPU0_BYPASS_REG(reg)	(NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
83 						+ (reg))
84 
85 #define CSUIDR_NUM_CMI(x)		(((x) & 0x3f000000) >> 24)
86 #define CSUIDR_NUM_DIR(x)		(((x) & 0x003f0000) >> 16)
87 #define CSUIDR_NUM_NCB(x)		(((x) & 0x00003f00) >> 8)
88 #define CSUIDR_NUM_CAI(x)		(((x) & 0x0000007f) >> 0)
89 
90 #define CSIDR_NUM_SF(x)			(((x) & 0x007c0000) >> 18)
91 
92 #define SNOOP_FILTER_ID(x)		(((x) << 16))
93 
94 #define CACHING_AGENT_BIT(x)		(((x) & 0x08000) >> 15)
95 #define CACHING_AGENT_TYPE(x)		(((x) & 0xf0000) >> 16)
96 
97 
98 typedef struct coh_ss_id {
99 	uint8_t num_coh_mem;
100 	uint8_t num_directory;
101 	uint8_t num_non_coh_bridge;
102 	uint8_t num_coh_agent;
103 	uint8_t num_snoop_filter;
104 } coh_ss_id_t;
105 
106 uint32_t init_ncore_ccu(void);
107 
108 #endif
109