1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 10 #include <plat_private.h> 11 12 #ifndef BITS_WMSK 13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) 14 #endif 15 16 enum plls_id { 17 APLL_ID = 0, 18 DPLL_ID, 19 CPLL_ID, 20 NPLL_ID, 21 GPLL_ID, 22 END_PLL_ID, 23 }; 24 25 enum pll_mode { 26 SLOW_MODE, 27 NORM_MODE, 28 DEEP_SLOW_MODE, 29 }; 30 31 /*************************************************************************** 32 * GRF 33 ***************************************************************************/ 34 #define GRF_SOC_CON(i) (0x0400 + (i) * 4) 35 #define GRF_PD_VO_CON0 0x0434 36 #define GRF_SOC_STATUS0 0x0480 37 #define GRF_CPU_STATUS0 0x0520 38 #define GRF_CPU_STATUS1 0x0524 39 #define GRF_SOC_NOC_CON0 0x0530 40 #define GRF_SOC_NOC_CON1 0x0534 41 42 #define CKECK_WFE_MSK 0x1 43 #define CKECK_WFI_MSK 0x10 44 #define CKECK_WFEI_MSK 0x11 45 46 #define GRF_SOC_CON2_NSWDT_RST_EN 12 47 48 /*************************************************************************** 49 * cru 50 ***************************************************************************/ 51 #define CRU_MODE 0xa0 52 #define CRU_MISC 0xa4 53 #define CRU_GLB_CNT_TH 0xb0 54 #define CRU_GLB_RST_ST 0xb4 55 #define CRU_GLB_SRST_FST 0xb8 56 #define CRU_GLB_SRST_SND 0xbc 57 #define CRU_GLB_RST_CON 0xc0 58 59 #define CRU_CLKSEL_CON 0x100 60 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4) 61 #define CRU_CLKSEL_CON_CNT 60 62 63 #define CRU_CLKGATE_CON 0x200 64 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) 65 #define CRU_CLKGATES_CON_CNT 18 66 67 #define CRU_SOFTRST_CON 0x300 68 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) 69 #define CRU_SOFTRSTS_CON_CNT 12 70 71 #define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8) 72 #define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8) 73 74 #define CRU_CONS_GATEID(i) (16 * (i)) 75 #define GATE_ID(reg, bit) ((reg) * 16 + (bit)) 76 77 #define CRU_GLB_SRST_FST_VALUE 0xfdb9 78 #define CRU_GLB_SRST_SND_VALUE 0xeca8 79 80 #define CRU_GLB_RST_TSADC_EXT 6 81 #define CRU_GLB_RST_WDT_EXT 7 82 83 #define CRU_GLB_CNT_RST_MSK 0xffff 84 #define CRU_GLB_CNT_RST_1MS 0x5DC0 85 86 #define CRU_GLB_RST_TSADC_FST BIT(0) 87 #define CRU_GLB_RST_WDT_FST BIT(1) 88 89 /*************************************************************************** 90 * pll 91 ***************************************************************************/ 92 #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) 93 #define PLL_CON(i) ((i) * 4) 94 #define PLL_CON_CNT 5 95 #define PLL_LOCK_MSK BIT(10) 96 #define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \ 97 2 : \ 98 ((id) == DPLL_ID ? 4 : 2 * (id))) 99 #define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id)) 100 101 #define PLL_LOCKED_TIMEOUT 600000U 102 103 /*************************************************************************** 104 * GPIO 105 ***************************************************************************/ 106 #define SWPORTA_DR 0x00 107 #define SWPORTA_DDR 0x04 108 #define GPIO_INTEN 0x30 109 #define GPIO_INT_STATUS 0x40 110 #define GPIO_NUMS 4 111 112 void clk_gate_con_save(uint32_t *clkgt_save); 113 void clk_gate_con_restore(uint32_t *clkgt_save); 114 void clk_gate_con_disable(void); 115 116 void px30_soc_reset_config(void); 117 118 #endif /* __SOC_H__ */ 119