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Searched refs:PCLK_TIMER1 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_bl_common.c31 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { in hikey_sp804_init()
32 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
37 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
40 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)); in hikey_sp804_init()
42 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
45 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0)); in hikey_sp804_init()
/trusted-firmware-a/plat/hisilicon/hikey/include/
A Dhi6220_regs_ao.h331 #define PCLK_TIMER1 (1 << 16) macro

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