1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PL011_H 8 #define PL011_H 9 10 #include <drivers/console.h> 11 12 /* PL011 Registers */ 13 #define UARTDR 0x000 14 #define UARTRSR 0x004 15 #define UARTECR 0x004 16 #define UARTFR 0x018 17 #define UARTIMSC 0x038 18 #define UARTRIS 0x03C 19 #define UARTICR 0x044 20 21 /* PL011 registers (out of the SBSA specification) */ 22 #if !PL011_GENERIC_UART 23 #define UARTILPR 0x020 24 #define UARTIBRD 0x024 25 #define UARTFBRD 0x028 26 #define UARTLCR_H 0x02C 27 #define UARTCR 0x030 28 #define UARTIFLS 0x034 29 #define UARTMIS 0x040 30 #define UARTDMACR 0x048 31 #endif /* !PL011_GENERIC_UART */ 32 33 /* Data status bits */ 34 #define UART_DATA_ERROR_MASK 0x0F00 35 36 /* Status reg bits */ 37 #define UART_STATUS_ERROR_MASK 0x0F 38 39 /* Flag reg bits */ 40 #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ 41 #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ 42 #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ 43 #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ 44 #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ 45 #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ 46 #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ 47 #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ 48 #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ 49 50 #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ 51 #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ 52 #define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ 53 54 /* Control reg bits */ 55 #if !PL011_GENERIC_UART 56 #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ 57 #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ 58 #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ 59 #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ 60 #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ 61 #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ 62 #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ 63 #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ 64 65 #if !defined(PL011_LINE_CONTROL) 66 /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ 67 #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) 68 #endif 69 70 /* Line Control Register Bits */ 71 #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ 72 #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 73 #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 74 #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 75 #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 76 #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ 77 #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ 78 #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ 79 #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ 80 #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ 81 82 #endif /* !PL011_GENERIC_UART */ 83 84 #ifndef __ASSEMBLER__ 85 86 #include <stdint.h> 87 88 /* 89 * Initialize a new PL011 console instance and register it with the console 90 * framework. The |console| pointer must point to storage that will be valid 91 * for the lifetime of the console, such as a global or static local variable. 92 * Its contents will be reinitialized from scratch. 93 */ 94 int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, 95 console_t *console); 96 97 #endif /*__ASSEMBLER__*/ 98 99 #endif /* PL011_H */ 100