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Searched refs:PLAT_ARM_GICD_BASE (Results 1 – 25 of 31) sorted by relevance

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/trusted-firmware-a/plat/arm/board/rdv1mc/
A Drdv1mc_plat.c32 .rt_owner_base = PLAT_ARM_GICD_BASE,
36 PLAT_ARM_GICD_BASE >> 16,
37 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
39 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
42 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
/trusted-firmware-a/services/spd/trusty/
A Dgeneric-arm64-smcall.c15 #ifndef PLAT_ARM_GICD_BASE
17 #define PLAT_ARM_GICD_BASE GICD_BASE macro
23 #error PLAT_ARM_GICD_BASE or GICD_BASE must be defined
68 return PLAT_ARM_GICD_BASE; in trusty_get_reg_base()
/trusted-firmware-a/plat/arm/board/rdn1edge/
A Drdn1edge_plat.c22 .rt_owner_base = PLAT_ARM_GICD_BASE,
26 PLAT_ARM_GICD_BASE >> 16,
27 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
/trusted-firmware-a/plat/arm/board/n1sdp/
A Dn1sdp_bl31_setup.c58 .rt_owner_base = PLAT_ARM_GICD_BASE,
62 PLAT_ARM_GICD_BASE >> 16,
63 PLAT_ARM_GICD_BASE >> 16
/trusted-firmware-a/plat/arm/css/sgm/include/
A Dsgm_base_platform_def.h41 #define PLAT_ARM_GICD_BASE 0x30000000 macro
48 PLAT_ARM_GICD_BASE, \
/trusted-firmware-a/include/plat/arm/css/common/aarch64/
A Dcss_macros.S20 mov_imm x16, PLAT_ARM_GICD_BASE
/trusted-firmware-a/plat/arm/board/sgi575/include/
A Dplatform_def.h42 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/rde1edge/include/
A Dplatform_def.h41 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/rdn1edge/include/
A Dplatform_def.h45 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/hisilicon/hikey/include/
A Dplatform_def.h48 #define PLAT_ARM_GICD_BASE 0xF6801000 macro
A Dplat_macros.S36 mov_imm x16, PLAT_ARM_GICD_BASE
/trusted-firmware-a/plat/arm/common/
A Darm_gicv2.c35 .gicd_base = PLAT_ARM_GICD_BASE,
A Darm_gicv3.c78 .gicd_base = PLAT_ARM_GICD_BASE,
/trusted-firmware-a/plat/arm/board/rdv1/include/
A Dplatform_def.h61 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/rdv1mc/include/
A Dplatform_def.h56 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/rdn2/include/
A Dplatform_def.h75 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/morello/include/
A Dplatform_def.h92 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/mediatek/mt8173/include/
A Dplatform_def.h118 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a/plat/arm/board/n1sdp/include/
A Dplatform_def.h135 #define PLAT_ARM_GICD_BASE 0x30000000 macro
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_bl31_setup.c49 .gicd_base = PLAT_ARM_GICD_BASE,
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_gicv3.c123 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; in plat_arm_gic_driver_init()
/trusted-firmware-a/plat/xilinx/zynqmp/include/
A Dplatform_def.h109 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a/plat/arm/board/tc/include/
A Dplatform_def.h230 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a/plat/arm/board/fvp_r/include/
A Dplatform_def.h250 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a/plat/arm/board/juno/include/
A Dplatform_def.h235 #define PLAT_ARM_GICD_BASE UL(0x2c010000) macro

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