| /trusted-firmware-a/plat/hisilicon/hikey/ |
| A D | hikey_pm.c | 64 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_on_finish()
88 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_off()
104 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
107 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
114 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
119 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
139 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
148 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
153 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend_finish()
168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey_get_sys_suspend_power_state()
[all …]
|
| /trusted-firmware-a/plat/rockchip/common/ |
| A D | plat_pm.c | 158 PLAT_MAX_OFF_STATE; in rockchip_validate_power_state()
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
222 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_off()
226 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_off()
249 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
255 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
261 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
264 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
286 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_on_finish()
324 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend_finish()
[all …]
|
| /trusted-firmware-a/plat/nxp/common/psci/ |
| A D | plat_psci.c | 175 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
195 PLAT_MAX_OFF_STATE) { in _pwr_suspend()
248 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
272 PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
349 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
357 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
365 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
375 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
395 req_state->pwr_domain_state[PLAT_MAX_LVL] = PLAT_MAX_OFF_STATE; in _pwr_state_sys_suspend()
396 req_state->pwr_domain_state[PLAT_SYS_LVL] = PLAT_MAX_OFF_STATE; in _pwr_state_sys_suspend()
[all …]
|
| /trusted-firmware-a/plat/renesas/common/ |
| A D | plat_pm.c | 81 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_on_finish()
103 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_off()
117 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend()
125 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
138 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend_finish()
161 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_pwr_down_wfi()
262 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
281 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/imx/common/ |
| A D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/hisilicon/hikey960/ |
| A D | hikey960_pm.c | 85 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_on_finish()
164 PLAT_MAX_OFF_STATE; in hikey960_validate_power_state()
195 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend()
198 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
216 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
272 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend_finish()
294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/hisilicon/poplar/ |
| A D | plat_pm.c | 77 PLAT_MAX_OFF_STATE); in poplar_pwr_domain_on_finish()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/xilinx/versal/ |
| A D | plat_psci.c | 198 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
214 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
215 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/nxp/soc-ls1028a/include/ |
| A D | soc.h | 132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) macro
133 #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
|
| /trusted-firmware-a/plat/xilinx/zynqmp/ |
| A D | plat_psci.c | 173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
184 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
185 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/ti/k3/common/ |
| A D | k3_psci.c | 91 assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in k3_pwr_domain_off()
107 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in k3_pwr_domain_off()
137 if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in k3_pwr_domain_off()
|
| /trusted-firmware-a/plat/ti/k3/board/generic/include/ |
| A D | board_def.h | 36 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/ti/k3/board/lite/include/ |
| A D | board_def.h | 38 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/intel/soc/common/ |
| A D | socfpga_psci.c | 192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/hisilicon/hikey/include/ |
| A D | platform_def.h | 40 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/allwinner/common/ |
| A D | sunxi_scpi_pm.c | 166 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_validate_power_state()
182 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
|
| /trusted-firmware-a/plat/amlogic/g12a/include/ |
| A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/amlogic/gxl/include/ |
| A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/amlogic/gxbb/include/ |
| A D | platform_def.h | 35 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/amlogic/axg/include/ |
| A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/imx/imx8qx/include/ |
| A D | platform_def.h | 27 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/rockchip/rk3288/include/ |
| A D | platform_def.h | 62 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/layerscape/board/ls1043/include/ |
| A D | ls_def.h | 93 #define PLAT_MAX_OFF_STATE LS_LOCAL_STATE_OFF macro
|
| /trusted-firmware-a/plat/imx/imx8qm/include/ |
| A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
|
| /trusted-firmware-a/plat/allwinner/common/include/ |
| A D | platform_def.h | 62 #define PLAT_MAX_OFF_STATE U(2) macro
|