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Searched refs:PLAT_MAX_RET_STATE (Results 1 – 25 of 77) sorted by relevance

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/trusted-firmware-a/plat/nxp/common/psci/
A Dplat_psci.c151 if (cpu_state == PLAT_MAX_RET_STATE) { in _pwr_cpu_standby()
184 == PLAT_MAX_RET_STATE) { in _pwr_suspend()
206 PLAT_MAX_RET_STATE) { in _pwr_suspend()
227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()
259 == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
285 PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
309 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend_finish()
352 PLAT_MAX_RET_STATE; in _pwr_state_validate()
360 PLAT_MAX_RET_STATE; in _pwr_state_validate()
368 PLAT_MAX_RET_STATE; in _pwr_state_validate()
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/trusted-firmware-a/plat/xilinx/versal/
A Dplat_psci.c62 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
66 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in versal_pwr_domain_suspend()
74 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend()
103 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish()
196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dimx8mq_psci.c30 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
31 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
36 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
105 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/trusted-firmware-a/plat/nxp/soc-ls1028a/include/
A Dsoc.h128 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
129 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a/plat/xilinx/zynqmp/
A Dplat_psci.c85 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in zynqmp_pwr_domain_suspend()
92 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend()
122 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish()
171 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
/trusted-firmware-a/plat/imx/common/
A Dimx8_psci.c45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/trusted-firmware-a/plat/nxp/soc-lx2160a/include/
A Dsoc.h106 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) macro
109 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
/trusted-firmware-a/plat/imx/imx8m/imx8mq/include/
A Dplatform_def.h27 #define PLAT_MAX_RET_STATE U(1) macro
29 #define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE
/trusted-firmware-a/plat/ti/k3/board/generic/include/
A Dboard_def.h37 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/ti/k3/board/lite/include/
A Dboard_def.h39 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/rockchip/common/
A Dplat_pm.c154 PLAT_MAX_RET_STATE; in rockchip_validate_power_state()
162 PLAT_MAX_RET_STATE; in rockchip_validate_power_state()
187 assert(cpu_state == PLAT_MAX_RET_STATE); in rockchip_cpu_standby()
/trusted-firmware-a/plat/hisilicon/hikey/include/
A Dplatform_def.h39 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/imx/imx8m/
A Dimx8m_psci_common.c78 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
79 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
/trusted-firmware-a/plat/amlogic/g12a/include/
A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/amlogic/gxl/include/
A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/amlogic/gxbb/include/
A Dplatform_def.h34 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/amlogic/axg/include/
A Dplatform_def.h31 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/imx/imx8qx/include/
A Dplatform_def.h28 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/rockchip/rk3288/include/
A Dplatform_def.h56 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/layerscape/board/ls1043/include/
A Dls_def.h87 #define PLAT_MAX_RET_STATE LS_LOCAL_STATE_RET macro
/trusted-firmware-a/plat/imx/imx8qm/include/
A Dplatform_def.h33 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/allwinner/common/include/
A Dplatform_def.h61 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/rockchip/rk3328/include/
A Dplatform_def.h58 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/rockchip/rk3399/include/
A Dplatform_def.h58 #define PLAT_MAX_RET_STATE U(1) macro
/trusted-firmware-a/plat/socionext/uniphier/include/
A Dplatform_def.h29 #define PLAT_MAX_RET_STATE U(1) macro

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