1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #if STM32MP_USE_STM32IMAGE 29 #ifdef AARCH32_SP_OPTEE 30 #define OPTEE_HEADER_IMAGE_NAME "teeh" 31 #define OPTEE_CORE_IMAGE_NAME "teex" 32 #define OPTEE_PAGED_IMAGE_NAME "teed" 33 #define OPTEE_HEADER_BINARY_TYPE U(0x20) 34 #define OPTEE_CORE_BINARY_TYPE U(0x21) 35 #define OPTEE_PAGED_BINARY_TYPE U(0x22) 36 #endif 37 38 /* SSBL = second stage boot loader */ 39 #define BL33_IMAGE_NAME "ssbl" 40 #define BL33_BINARY_TYPE U(0x0) 41 #else /* STM32MP_USE_STM32IMAGE */ 42 #define FIP_IMAGE_NAME "fip" 43 #endif /* STM32MP_USE_STM32IMAGE */ 44 45 #define STM32MP_PRIMARY_CPU U(0x0) 46 #define STM32MP_SECONDARY_CPU U(0x1) 47 48 #define PLATFORM_CLUSTER_COUNT U(1) 49 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 50 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 51 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 52 PLATFORM_CLUSTER0_CORE_COUNT) 53 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 54 55 #define MAX_IO_DEVICES U(4) 56 #define MAX_IO_HANDLES U(4) 57 #define MAX_IO_BLOCK_DEVICES U(1) 58 #define MAX_IO_MTD_DEVICES U(1) 59 60 /******************************************************************************* 61 * BL2 specific defines. 62 ******************************************************************************/ 63 /* 64 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 65 * size plus a little space for growth. 66 */ 67 #define BL2_BASE STM32MP_BL2_BASE 68 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 69 STM32MP_BL2_SIZE) 70 71 /******************************************************************************* 72 * BL32 specific defines. 73 ******************************************************************************/ 74 #if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) 75 #if ENABLE_PIE 76 #define BL32_BASE 0 77 #define BL32_LIMIT STM32MP_BL32_SIZE 78 #else 79 #define BL32_BASE STM32MP_BL32_BASE 80 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 81 STM32MP_BL32_SIZE) 82 #endif 83 #endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */ 84 85 /******************************************************************************* 86 * BL33 specific defines. 87 ******************************************************************************/ 88 #define BL33_BASE STM32MP_BL33_BASE 89 90 /* 91 * Load address of BL33 for this platform port 92 */ 93 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 94 95 /* Needed by STM32CubeProgrammer support */ 96 #define DWL_BUFFER_BASE (STM32MP_DDR_BASE + U(0x08000000)) 97 #define DWL_BUFFER_SIZE U(0x08000000) 98 99 /* 100 * SSBL offset in case it's stored in eMMC boot partition. 101 * We can fix it to 256K because TF-A size can't be bigger than SRAM 102 */ 103 #define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000) 104 105 /******************************************************************************* 106 * DTB specific defines. 107 ******************************************************************************/ 108 #define DTB_BASE STM32MP_DTB_BASE 109 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 110 STM32MP_DTB_SIZE) 111 112 /******************************************************************************* 113 * Platform specific page table and MMU setup constants 114 ******************************************************************************/ 115 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 116 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 117 118 /******************************************************************************* 119 * Declarations and constants to access the mailboxes safely. Each mailbox is 120 * aligned on the biggest cache line size in the platform. This is known only 121 * to the platform as it might have a combination of integrated and external 122 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 123 * line at any cache level. They could belong to different cpus/clusters & 124 * get written while being protected by different locks causing corruption of 125 * a valid mailbox address. 126 ******************************************************************************/ 127 #define CACHE_WRITEBACK_SHIFT 6 128 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 129 130 /* 131 * Secure Interrupt: based on the standard ARM mapping 132 */ 133 #define ARM_IRQ_SEC_PHY_TIMER U(29) 134 135 #define ARM_IRQ_SEC_SGI_0 U(8) 136 #define ARM_IRQ_SEC_SGI_1 U(9) 137 #define ARM_IRQ_SEC_SGI_2 U(10) 138 #define ARM_IRQ_SEC_SGI_3 U(11) 139 #define ARM_IRQ_SEC_SGI_4 U(12) 140 #define ARM_IRQ_SEC_SGI_5 U(13) 141 #define ARM_IRQ_SEC_SGI_6 U(14) 142 #define ARM_IRQ_SEC_SGI_7 U(15) 143 144 #define STM32MP1_IRQ_TZC400 U(36) 145 #define STM32MP1_IRQ_TAMPSERRS U(229) 146 #define STM32MP1_IRQ_AXIERRIRQ U(244) 147 148 /* 149 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 150 * terminology. On a GICv2 system or mode, the lists will be merged and treated 151 * as Group 0 interrupts. 152 */ 153 #define PLATFORM_G1S_PROPS(grp) \ 154 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 155 GIC_HIGHEST_SEC_PRIORITY, \ 156 grp, GIC_INTR_CFG_LEVEL), \ 157 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 158 GIC_HIGHEST_SEC_PRIORITY, \ 159 grp, GIC_INTR_CFG_LEVEL), \ 160 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 161 GIC_HIGHEST_SEC_PRIORITY, \ 162 grp, GIC_INTR_CFG_LEVEL), \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 164 GIC_HIGHEST_SEC_PRIORITY, \ 165 grp, GIC_INTR_CFG_EDGE), \ 166 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 167 GIC_HIGHEST_SEC_PRIORITY, \ 168 grp, GIC_INTR_CFG_EDGE), \ 169 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 170 GIC_HIGHEST_SEC_PRIORITY, \ 171 grp, GIC_INTR_CFG_EDGE), \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 173 GIC_HIGHEST_SEC_PRIORITY, \ 174 grp, GIC_INTR_CFG_EDGE), \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 176 GIC_HIGHEST_SEC_PRIORITY, \ 177 grp, GIC_INTR_CFG_EDGE), \ 178 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 179 GIC_HIGHEST_SEC_PRIORITY, \ 180 grp, GIC_INTR_CFG_EDGE) 181 182 #define PLATFORM_G0_PROPS(grp) \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 184 GIC_HIGHEST_SEC_PRIORITY, \ 185 grp, GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 187 GIC_HIGHEST_SEC_PRIORITY, \ 188 grp, GIC_INTR_CFG_EDGE) 189 190 /* 191 * Power 192 */ 193 #define PLAT_MAX_PWR_LVL U(1) 194 195 /* Local power state for power domains in Run state. */ 196 #define ARM_LOCAL_STATE_RUN U(0) 197 /* Local power state for retention. Valid only for CPU power domains */ 198 #define ARM_LOCAL_STATE_RET U(1) 199 /* Local power state for power-down. Valid for CPU and cluster power domains */ 200 #define ARM_LOCAL_STATE_OFF U(2) 201 /* 202 * This macro defines the deepest retention state possible. 203 * A higher state id will represent an invalid or a power down state. 204 */ 205 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 206 /* 207 * This macro defines the deepest power down states possible. Any state ID 208 * higher than this is invalid. 209 */ 210 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 211 212 /******************************************************************************* 213 * Size of the per-cpu data in bytes that should be reserved in the generic 214 * per-cpu data structure for the FVP port. 215 ******************************************************************************/ 216 #define PLAT_PCPU_DATA_SIZE 2 217 218 /******************************************************************************* 219 * Number of parallel entry slots in SMT SCMI server entry context. For this 220 * platform, SCMI server is reached through SMC only, hence the number of 221 * entry slots. 222 ******************************************************************************/ 223 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 224 225 #endif /* PLATFORM_DEF_H */ 226