1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TZC_DMC500_H 8 #define TZC_DMC500_H 9 10 #include <drivers/arm/tzc_common.h> 11 #include <lib/utils_def.h> 12 13 #define SI_STATUS_OFFSET U(0x000) 14 #define SI_STATE_CTRL_OFFSET U(0x030) 15 #define SI_FLUSH_CTRL_OFFSET U(0x034) 16 #define SI_INT_CONTROL_OFFSET U(0x048) 17 18 #define SI_INT_STATUS_OFFSET U(0x004) 19 #define SI_TZ_FAIL_ADDRESS_LOW_OFFSET U(0x008) 20 #define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET U(0x00c) 21 #define SI_FAIL_CONTROL_OFFSET U(0x010) 22 #define SI_FAIL_ID_OFFSET U(0x014) 23 #define SI_INT_CLR_OFFSET U(0x04c) 24 25 /* 26 * DMC-500 has 2 system interfaces each having a similar set of regs 27 * to configure each interface. 28 */ 29 #define SI0_BASE U(0x0000) 30 #define SI1_BASE U(0x0200) 31 32 /* Bit positions of SIx_SI_STATUS */ 33 #define SI_EMPTY_SHIFT 1 34 #define SI_STALL_ACK_SHIFT 0 35 #define SI_EMPTY_MASK U(0x01) 36 #define SI_STALL_ACK_MASK U(0x01) 37 38 /* Bit positions of SIx_SI_INT_STATUS */ 39 #define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18 40 #define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16 41 #define PMU_REQ_INT_STATUS_SHIFT 2 42 #define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1 43 #define FAILED_ACCESS_INT_STATUS_SHIFT 0 44 #define PMU_REQ_INT_OVERFLOW_STATUS_MASK U(0x1) 45 #define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK U(0x1) 46 #define PMU_REQ_INT_STATUS_MASK U(0x1) 47 #define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK U(0x1) 48 #define FAILED_ACCESS_INT_STATUS_MASK U(0x1) 49 50 /* Bit positions of SIx_TZ_FAIL_CONTROL */ 51 #define DIRECTION_SHIFT 24 52 #define NON_SECURE_SHIFT 21 53 #define PRIVILEGED_SHIFT 20 54 #define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3 55 #define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2 56 #define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 1 57 #define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0 58 #define DIRECTION_MASK U(0x1) 59 #define NON_SECURE_MASK U(0x1) 60 #define PRIVILEGED_MASK U(0x1) 61 #define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK U(0x1) 62 #define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK U(0x1) 63 #define FAILED_ACCESS_INT_TZ_FAIL_MASK U(0x1) 64 #define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK U(0x1) 65 66 /* Bit positions of SIx_FAIL_STATUS */ 67 #define FAIL_ID_VNET_SHIFT 24 68 #define FAIL_ID_ID_SHIFT 0 69 #define FAIL_ID_VNET_MASK U(0xf) 70 #define FAIL_ID_ID_MASK U(0xffffff) 71 72 /* Bit positions of SIx_SI_STATE_CONTRL */ 73 #define SI_STALL_REQ_GO 0x0 74 #define SI_STALL_REQ_STALL 0x1 75 76 /* Bit positions of SIx_SI_FLUSH_CONTROL */ 77 #define SI_FLUSH_REQ_INACTIVE 0x0 78 #define SI_FLUSH_REQ_ACTIVE 0x1 79 #define SI_FLUSH_REQ_MASK 0x1 80 81 /* Bit positions of SIx_SI_INT_CONTROL */ 82 #define PMU_REQ_INT_EN_SHIFT 2 83 #define OVERLAP_DETECT_INT_EN_SHIFT 1 84 #define FAILED_ACCESS_INT_EN_SHIFT 0 85 #define PMU_REQ_INT_EN_MASK U(0x1) 86 #define OVERLAP_DETECT_INT_EN_MASK U(0x1) 87 #define FAILED_ACCESS_INT_EN_MASK U(0x1) 88 #define PMU_REQ_INT_EN U(0x1) 89 #define OVERLAP_DETECT_INT_EN U(0x1) 90 #define FAILED_ACCESS_INT_EN U(0x1) 91 92 /* Bit positions of SIx_SI_INT_CLR */ 93 #define PMU_REQ_OFLOW_CLR_SHIFT 18 94 #define FAILED_ACCESS_OFLOW_CLR_SHIFT 16 95 #define PMU_REQ_INT_CLR_SHIFT 2 96 #define FAILED_ACCESS_INT_CLR_SHIFT 0 97 #define PMU_REQ_OFLOW_CLR_MASK U(0x1) 98 #define FAILED_ACCESS_OFLOW_CLR_MASK U(0x1) 99 #define PMU_REQ_INT_CLR_MASK U(0x1) 100 #define FAILED_ACCESS_INT_CLR_MASK U(0x1) 101 #define PMU_REQ_OFLOW_CLR U(0x1) 102 #define FAILED_ACCESS_OFLOW_CLR U(0x1) 103 #define PMU_REQ_INT_CLR U(0x1) 104 #define FAILED_ACCESS_INT_CLR U(0x1) 105 106 /* Macro to get the correct base register for a system interface */ 107 #define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE) 108 109 #define MAX_SYS_IF_COUNT U(2) 110 #define MAX_REGION_VAL 8 111 112 /* DMC-500 supports striping across a max of 4 DMC instances */ 113 #define MAX_DMC_COUNT 4 114 115 /* Consist of part_number_1 and part_number_0 */ 116 #define DMC500_PERIPHERAL_ID U(0x0450) 117 118 /* Filter enable bits in a TZC */ 119 #define TZC_DMC500_REGION_ATTR_F_EN_MASK U(0x1) 120 121 /* Length of registers for configuring each region */ 122 #define TZC_DMC500_REGION_SIZE U(0x018) 123 124 #ifndef __ASSEMBLER__ 125 126 #include <stdint.h> 127 128 /* 129 * Contains the base addresses of all the DMC instances. 130 */ 131 typedef struct tzc_dmc500_driver_data { 132 uintptr_t dmc_base[MAX_DMC_COUNT]; 133 int dmc_count; 134 unsigned int sys_if_count; 135 } tzc_dmc500_driver_data_t; 136 137 void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data); 138 void tzc_dmc500_configure_region0(unsigned int sec_attr, 139 unsigned int nsaid_permissions); 140 void tzc_dmc500_configure_region(unsigned int region_no, 141 unsigned long long region_base, 142 unsigned long long region_top, 143 unsigned int sec_attr, 144 unsigned int nsaid_permissions); 145 void tzc_dmc500_set_action(unsigned int action); 146 void tzc_dmc500_config_complete(void); 147 int tzc_dmc500_verify_complete(void); 148 149 150 #endif /* __ASSEMBLER__ */ 151 #endif /* TZC_DMC500_H */ 152