Searched refs:PSCI_CPU_PWR_LVL (Results 1 – 14 of 14) sorted by relevance
87 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()122 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_stats_update_pwr_up()123 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); in psci_stats_update_pwr_up()126 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, in psci_stats_update_pwr_up()142 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()210 if (pwrlvl > PSCI_CPU_PWR_LVL) { in psci_get_stat()213 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) in psci_get_stat()
76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),211 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_set_req_local_pwr_state()212 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()246 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_get_req_local_pwr_states()311 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); in psci_get_target_local_pwr_states()315 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_get_target_local_pwr_states()337 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); in psci_set_target_local_pwr_states()366 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) { in psci_get_parent_pwr_domain_nodes()384 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_set_pwr_domains_to_run()433 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()[all …]
47 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()140 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()170 if (level == (int) PSCI_CPU_PWR_LVL) in populate_power_domain_tree()
95 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_cpu_suspend()123 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); in psci_cpu_suspend()226 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) in psci_affinity_info()
26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
287 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]) != 0)); in psci_cpu_suspend_finish()
100 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL)); in plat_psci_stat_get_residency()104 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()112 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in plat_psci_stat_get_residency()
19 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
214 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
184 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
30 #define PSCI_CPU_PWR_LVL U(0) macro
330 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
328 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
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