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Searched refs:PU_PGC_DN_TRG (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a/plat/imx/imx8m/imx8mp/
A Dgpc.c274 mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | in imx_gpc_pm_domain_enable()
277 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ | in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
286 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/include/
A Dgpc_reg.h29 #define PU_PGC_DN_TRG 0x104 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mn/include/
A Dgpc_reg.h29 #define PU_PGC_DN_TRG 0x104 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mm/include/
A Dgpc_reg.h29 #define PU_PGC_DN_TRG 0x104 macro
/trusted-firmware-a/plat/imx/imx8m/imx8mp/include/
A Dgpc_reg.h30 #define PU_PGC_DN_TRG 0xE4 macro

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