Searched refs:SCR (Results 1 – 11 of 11) sorted by relevance
| /trusted-firmware-a/include/arch/aarch32/ |
| A D | smccc_macros.S | 27 ldcopr r4, SCR
29 stcopr r2, SCR
60 stcopr r4, SCR
86 ldcopr r4, SCR
136 stcopr r1, SCR
169 ldcopr r4, SCR
171 stcopr r2, SCR
201 stcopr r4, SCR
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| A D | el3_common_macros.S | 47 stcopr r0, SCR
245 ldcopr r0, SCR
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| A D | arch_helpers.h | 227 DEFINE_COPROCR_RW_FUNCS(scr, SCR) in DEFINE_SYSREG_RW_FUNCS()
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| A D | arch.h | 511 #define SCR p15, 0, c1, c1, 0 macro
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| /trusted-firmware-a/bl32/sp_min/aarch32/ |
| A D | entrypoint.S | 34 ldcopr \reg, SCR
37 stcopr \reg, SCR
221 stcopr r0, SCR
265 stcopr r0, SCR
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| /trusted-firmware-a/bl1/aarch32/ |
| A D | bl1_exceptions.S | 41 ldcopr r8, SCR
110 stcopr r0, SCR
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| /trusted-firmware-a/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
156 for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | psci-lib-integration-guide.rst.txt | 102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
156 for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
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| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 254 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
255 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
283 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 254 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
255 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
283 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
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| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.tex | 7985 SCR\_EL3. If this function returns TWED\_DISABLED or is left unimplemented, this
7987 SCR\_EL3, there are similar fields in HCR\_EL2, SCTLR\_EL2, and SCTLR\_EL1 to adjust
9395 Values for certain system registers like SCR and SCTLR cannot be
9412 registers: R0 \sphinxhyphen{} R3, LR (R14), SCR, SPSR, SCTLR.
9459 for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR\_EL3
27484 …o AArch64 by setting the \sphinxcode{\sphinxupquote{SCR.RW}} bit. The \sphinxcode{\sphinxupquote{S…
27527 \sphinxcode{\sphinxupquote{SCR}}. The \sphinxcode{\sphinxupquote{SCR.SIF}} bit is set to disable in…
30861 …uration Register at EL3 (\sphinxcode{\sphinxupquote{SCR\_EL3.FIQ}} and \sphinxcode{\sphinxupquote{…
31269 \sphinxcode{\sphinxupquote{SCR\_EL3}} register prior to returning from the EL3 exception level.
61669 Determine client EL from NS context’s SCR\_EL3
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