| /trusted-firmware-a/plat/arm/board/fvp_r/ |
| A D | fvp_r_misc_helpers.S | 18 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
30 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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| A D | fvp_r_bl1_main.c | 199 assert((val & SCTLR_M_BIT) != 0U); in bl1_main()
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| /trusted-firmware-a/lib/xlat_mpu/aarch64/ |
| A D | xlat_mpu_arch.c | 43 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; in is_mpu_enabled_ctx()
46 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; in is_mpu_enabled_ctx()
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| A D | enable_mpu.S | 18 tst x1, #SCTLR_M_BIT
41 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
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| /trusted-firmware-a/lib/xlat_tables/aarch32/ |
| A D | xlat_tables.c | 78 assert((read_sctlr() & SCTLR_M_BIT) == 0U); in enable_mmu_svc_mon()
125 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; in enable_mmu_svc_mon()
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| A D | nonlpae_tables.c | 516 assert((read_sctlr() & SCTLR_M_BIT) == 0U); in enable_mmu_svc_mon()
551 sctlr |= SCTLR_M_BIT; in enable_mmu_svc_mon()
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| /trusted-firmware-a/lib/xlat_tables_v2/aarch64/ |
| A D | enable_mmu.S | 41 tst x1, #SCTLR_M_BIT
73 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
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| A D | xlat_tables_arch.c | 152 return (read_sctlr_el1() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
155 return (read_sctlr_el2() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
159 return (read_sctlr_el3() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
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| /trusted-firmware-a/lib/xlat_tables_v2/aarch32/ |
| A D | enable_mmu.S | 19 tst r1, #SCTLR_M_BIT
57 ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT)
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| A D | xlat_tables_arch.c | 79 return (read_sctlr() & SCTLR_M_BIT) != 0U; in is_mmu_enabled_ctx()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| A D | mce.c | 197 if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) { in mce_enable_strict_checking()
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| /trusted-firmware-a/lib/aarch64/ |
| A D | misc_helpers.S | 173 tst tmp1, #SCTLR_M_BIT
421 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
433 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
443 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
455 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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| /trusted-firmware-a/lib/cpus/aarch64/ |
| A D | wa_cve_2017_5715_mmu.S | 23 bic x1, x1, #SCTLR_M_BIT
27 orr x1, x1, #SCTLR_M_BIT
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| /trusted-firmware-a/lib/xlat_tables/aarch64/ |
| A D | xlat_tables.c | 156 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U); \
199 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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| /trusted-firmware-a/lib/aarch32/ |
| A D | misc_helpers.S | 176 mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
192 ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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| /trusted-firmware-a/plat/nvidia/tegra/lib/debug/ |
| A D | profiler.c | 100 ((read_sctlr_el3() & SCTLR_M_BIT) != U(0))) { in boot_profiler_add_record()
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| /trusted-firmware-a/plat/st/common/ |
| A D | stm32mp_common.c | 75 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; in stm32mp_lock_available()
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| /trusted-firmware-a/plat/brcm/common/ |
| A D | brcm_bl2_setup.c | 100 if (!(read_sctlr_el1() & SCTLR_M_BIT)) { in bcm_bl2_plat_arch_setup()
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| /trusted-firmware-a/plat/rockchip/rk3399/drivers/pmu/ |
| A D | plat_pmu_macros.S | 83 bic x10, x9, #(SCTLR_M_BIT)
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| /trusted-firmware-a/bl1/ |
| A D | bl1_main.c | 102 assert((val & SCTLR_M_BIT) != 0); in bl1_main()
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| /trusted-firmware-a/services/std_svc/spm_mm/ |
| A D | spm_mm_setup.c | 155 SCTLR_M_BIT in spm_sp_setup()
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 74 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-3.rst.txt | 74 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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| /trusted-firmware-a/include/arch/aarch64/ |
| A D | arch_helpers.h | 651 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
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| /trusted-firmware-a/include/arch/aarch32/ |
| A D | arch.h | 159 #define SCTLR_M_BIT (U(1) << 0) macro
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