Searched refs:SDCR (Results 1 – 14 of 14) sorted by relevance
| /trusted-firmware-a/lib/extensions/mtpmu/aarch32/ |
| A D | mtpmu.S | 79 ldcopr r0, SDCR
82 stcopr r0, SDCR
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| /trusted-firmware-a/include/arch/aarch32/ |
| A D | smccc_macros.S | 95 ldcopr r5, SDCR
154 ldcopr r1, SDCR
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| A D | el3_common_macros.S | 150 stcopr r0, SDCR
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| A D | arch_helpers.h | 286 DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR) in DEFINE_SYSREG_RW_FUNCS()
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| A D | arch.h | 514 #define SDCR p15, 0, c1, c3, 1 macro
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-2.rst | 54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-2.rst.txt | 54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
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| /trusted-firmware-a/docs/process/ |
| A D | security-hardening.rst | 117 In Aarch32 execution state the ``MDCR_EL3`` alias is the ``SDCR`` register,
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/process/ |
| A D | security-hardening.rst.txt | 117 In Aarch32 execution state the ``MDCR_EL3`` alias is the ``SDCR`` register,
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| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 300 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 300 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | change-log.md.txt | 2612 the counter gets disabled by setting `SDCR.SCCD` bit on CPU cold/warm
3774 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
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| /trusted-firmware-a/docs/ |
| A D | change-log.md | 2612 the counter gets disabled by setting `SDCR.SCCD` bit on CPU cold/warm
3774 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
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| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.tex | 13152 …the \sphinxcode{\sphinxupquote{MDCR\_EL3}} alias is the \sphinxcode{\sphinxupquote{SDCR}} register,
27554 \sphinxcode{\sphinxupquote{SDCR}}. The \sphinxcode{\sphinxupquote{SDCR.SPD}} field is set to disabl…
44756 macro. Here the affected bits are \sphinxcode{\sphinxupquote{SDCR.SPD}}, which should also be assig…
60272 the counter gets disabled by setting \sphinxcode{\sphinxupquote{SDCR.SCCD}} bit on CPU cold/warm
62855 Debug registers MDCR\sphinxhyphen{}EL3/SDCR and MDCR\_EL2/HDCR are initialised to avoid
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