Searched refs:SMCCC_ARCH_WORKAROUND_1 (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a/services/arm_arch_svc/
A D	arm_arch_svc_setup.c	41 case SMCCC_ARCH_WORKAROUND_1: in smccc_arch_features() 127 case SMCCC_ARCH_WORKAROUND_1: in arm_arch_svc_smc_handler()
/trusted-firmware-a/include/services/
A D	arm_arch_svc.h	13 #define SMCCC_ARCH_WORKAROUND_1 U(0x80008000) macro
/trusted-firmware-a/docs/security_advisories/
A D	security-advisory-tfv-6.rst	67 (``SMCCC_ARCH_WORKAROUND_1``) for use by normal world privileged software. This 69 Details of ``SMCCC_ARCH_WORKAROUND_1`` can be found in the `CVE-2017-5715 74 ``SMCCC_ARCH_WORKAROUND_1`` SMCs on Cortex-A57, using both the "MMU 77 Convention (SMCCC) from AArch64. For the ``SMCCC_ARCH_WORKAROUND_1`` cases, the 95 | ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable" | 386 | 99 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/
A D	security-advisory-tfv-6.rst.txt	67 (``SMCCC_ARCH_WORKAROUND_1``) for use by normal world privileged software. This 69 Details of ``SMCCC_ARCH_WORKAROUND_1`` can be found in the `CVE-2017-5715 74 ``SMCCC_ARCH_WORKAROUND_1`` SMCs on Cortex-A57, using both the "MMU 77 Convention (SMCCC) from AArch64. For the ``SMCCC_ARCH_WORKAROUND_1`` cases, the 95 | ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable" | 386 | 99 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |
/trusted-firmware-a/lib/cpus/aarch64/
A D	wa_cve_2017_5715_mmu.S	44 orr w1, wzr, #SMCCC_ARCH_WORKAROUND_1
A D	wa_cve_2017_5715_bpiall.S	317 orr w2, wzr, #SMCCC_ARCH_WORKAROUND_1

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