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Searched refs:SUNXI_R_CPUCFG_BASE (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a/plat/allwinner/sun50i_h6/include/
A Dsunxi_cpucfg.h22 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
23 #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
27 #define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
28 #define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
29 #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
30 #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
A Dsunxi_mmap.h57 #define SUNXI_R_CPUCFG_BASE 0x07000400 macro
/trusted-firmware-a/plat/allwinner/sun50i_h616/include/
A Dsunxi_cpucfg.h22 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
23 #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
27 #define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
28 #define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
29 #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
30 #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
A Dsunxi_mmap.h36 #define SUNXI_R_CPUCFG_BASE 0x07000400 macro
/trusted-firmware-a/plat/allwinner/sun50i_a64/include/
A Dsunxi_cpucfg.h28 #define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000)
29 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4)
30 #define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
31 #define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0)
32 #define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4)
33 #define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)
34 #define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
A Dsunxi_mmap.h66 #define SUNXI_R_CPUCFG_BASE 0x01f01c00 macro
/trusted-firmware-a/plat/allwinner/sun50i_r329/include/
A Dsunxi_cpucfg.h23 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
24 #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
A Dsunxi_mmap.h47 #define SUNXI_R_CPUCFG_BASE 0x07000400 macro
/trusted-firmware-a/plat/allwinner/sun50i_a64/
A Dsunxi_power.c231 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) in sunxi_cpu_power_off_self()
249 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in sunxi_cpu_power_off_self()
/trusted-firmware-a/plat/allwinner/common/
A Dsunxi_scpi_pm.c218 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in sunxi_set_scpi_psci_ops()

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