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Searched refs:TEGRA_RNG1_BASE (Results 1 – 6 of 6) sorted by relevance

/trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/se/
A Dse.c467 se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT); in tegra_se_suspend()
505 mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); in tegra_se_resume()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c132 se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + in tegra_soc_pwr_domain_suspend()
413 mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, in tegra_soc_pwr_domain_on_finish()
A Dplat_setup.c95 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
/trusted-firmware-a/plat/nvidia/tegra/include/t186/
A Dtegra_def.h225 #define TEGRA_RNG1_BASE U(0x03AE0000) macro
/trusted-firmware-a/plat/nvidia/tegra/include/t194/
A Dtegra_def.h187 #define TEGRA_RNG1_BASE U(0x03AE0000) macro
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_setup.c115 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */

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