1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef TEGRA_DEF_H
9 #define TEGRA_DEF_H
10 
11 #include <lib/utils_def.h>
12 
13 /*******************************************************************************
14  * Platform BL31 specific defines.
15  ******************************************************************************/
16 #define BL31_SIZE			U(0x40000)
17 
18 /*******************************************************************************
19  * MCE apertures used by the ARI interface
20  *
21  * Aperture 0 - Cpu0 (ARM Cortex A-57)
22  * Aperture 1 - Cpu1 (ARM Cortex A-57)
23  * Aperture 2 - Cpu2 (ARM Cortex A-57)
24  * Aperture 3 - Cpu3 (ARM Cortex A-57)
25  * Aperture 4 - Cpu4 (Denver15)
26  * Aperture 5 - Cpu5 (Denver15)
27  ******************************************************************************/
28 #define MCE_ARI_APERTURE_0_OFFSET	U(0x0)
29 #define MCE_ARI_APERTURE_1_OFFSET	U(0x10000)
30 #define MCE_ARI_APERTURE_2_OFFSET	U(0x20000)
31 #define MCE_ARI_APERTURE_3_OFFSET	U(0x30000)
32 #define MCE_ARI_APERTURE_4_OFFSET	U(0x40000)
33 #define MCE_ARI_APERTURE_5_OFFSET	U(0x50000)
34 #define MCE_ARI_APERTURE_OFFSET_MAX	MCE_APERTURE_5_OFFSET
35 
36 /* number of apertures */
37 #define MCE_ARI_APERTURES_MAX		U(6)
38 
39 /* each ARI aperture is 64KB */
40 #define MCE_ARI_APERTURE_SIZE		U(0x10000)
41 
42 /*******************************************************************************
43  * CPU core id macros for the MCE_ONLINE_CORE ARI
44  ******************************************************************************/
45 #define MCE_CORE_ID_MAX			U(8)
46 #define MCE_CORE_ID_MASK		U(0x7)
47 
48 /*******************************************************************************
49  * These values are used by the PSCI implementation during the `CPU_SUSPEND`
50  * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
51  * parameter.
52  ******************************************************************************/
53 #define PSTATE_ID_CORE_IDLE		U(6)
54 #define PSTATE_ID_CORE_POWERDN		U(7)
55 #define PSTATE_ID_SOC_POWERDN		U(2)
56 
57 /*******************************************************************************
58  * Platform power states (used by PSCI framework)
59  *
60  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
61  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
62  ******************************************************************************/
63 #define PLAT_MAX_RET_STATE		U(1)
64 #define PLAT_MAX_OFF_STATE		U(8)
65 
66 /*******************************************************************************
67  * Chip specific page table and MMU setup constants
68  ******************************************************************************/
69 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 35)
70 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 35)
71 
72 /*******************************************************************************
73  * Secure IRQ definitions
74  ******************************************************************************/
75 #define TEGRA186_TOP_WDT_IRQ		U(49)
76 #define TEGRA186_AON_WDT_IRQ		U(50)
77 
78 #define TEGRA186_SEC_IRQ_TARGET_MASK	U(0xF3) /* 4 A57 - 2 Denver */
79 
80 /*******************************************************************************
81  * Clock identifier for the SE device
82  ******************************************************************************/
83 #define TEGRA186_CLK_SE			U(103)
84 #define TEGRA_CLK_SE			TEGRA186_CLK_SE
85 
86 /*******************************************************************************
87  * Tegra Miscellanous register constants
88  ******************************************************************************/
89 #define TEGRA_MISC_BASE			U(0x00100000)
90 #define  HARDWARE_REVISION_OFFSET	U(0x4)
91 
92 #define  MISCREG_PFCFG			U(0x200C)
93 
94 /*******************************************************************************
95  * Tegra TSA Controller constants
96  ******************************************************************************/
97 #define TEGRA_TSA_BASE			U(0x02400000)
98 
99 /*******************************************************************************
100  * TSA configuration registers
101  ******************************************************************************/
102 #define TSA_CONFIG_STATIC0_CSW_SESWR			U(0x4010)
103 #define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		U(0x1100)
104 #define TSA_CONFIG_STATIC0_CSW_ETRW			U(0x4038)
105 #define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		U(0x1100)
106 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			U(0x5010)
107 #define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		U(0x1100)
108 #define TSA_CONFIG_STATIC0_CSW_AXISW			U(0x7008)
109 #define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		U(0x1100)
110 #define TSA_CONFIG_STATIC0_CSW_HDAW			U(0xA008)
111 #define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		U(0x100)
112 #define TSA_CONFIG_STATIC0_CSW_AONDMAW			U(0xB018)
113 #define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		U(0x1100)
114 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW			U(0xD018)
115 #define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		U(0x1100)
116 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			U(0xD028)
117 #define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		U(0x1100)
118 #define TSA_CONFIG_STATIC0_CSW_APEDMAW			U(0x12018)
119 #define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		U(0x1100)
120 #define TSA_CONFIG_STATIC0_CSW_UFSHCW			U(0x13008)
121 #define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		U(0x1100)
122 #define TSA_CONFIG_STATIC0_CSW_AFIW			U(0x13018)
123 #define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		U(0x1100)
124 #define TSA_CONFIG_STATIC0_CSW_SATAW			U(0x13028)
125 #define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		U(0x1100)
126 #define TSA_CONFIG_STATIC0_CSW_EQOSW			U(0x13038)
127 #define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		U(0x1100)
128 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		U(0x15008)
129 #define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		U(0x1100)
130 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		U(0x15018)
131 #define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	U(0x1100)
132 
133 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(ULL(0x3) << 11)
134 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(ULL(0) << 11)
135 
136 /*******************************************************************************
137  * Tegra General Purpose Centralised DMA constants
138  ******************************************************************************/
139 #define TEGRA_GPCDMA_BASE		ULL(0x2610000)
140 
141 /*******************************************************************************
142  * Tegra Memory Controller constants
143  ******************************************************************************/
144 #define TEGRA_MC_STREAMID_BASE		U(0x02C00000)
145 #define TEGRA_MC_BASE			U(0x02C10000)
146 
147 /* General Security Carveout register macros */
148 #define MC_GSC_CONFIG_REGS_SIZE		U(0x40)
149 #define MC_GSC_LOCK_CFG_SETTINGS_BIT	(U(1) << 1)
150 #define MC_GSC_ENABLE_TZ_LOCK_BIT	(ULL(1) << 0)
151 #define MC_GSC_SIZE_RANGE_4KB_SHIFT	U(27)
152 #define MC_GSC_BASE_LO_SHIFT		U(12)
153 #define MC_GSC_BASE_LO_MASK		U(0xFFFFF)
154 #define MC_GSC_BASE_HI_SHIFT		U(0)
155 #define MC_GSC_BASE_HI_MASK		U(3)
156 #define MC_GSC_ENABLE_CPU_SECURE_BIT    (U(1) << 31)
157 
158 /* TZDRAM carveout configuration registers */
159 #define MC_SECURITY_CFG0_0		U(0x70)
160 #define MC_SECURITY_CFG1_0		U(0x74)
161 #define MC_SECURITY_CFG3_0		U(0x9BC)
162 
163 #define MC_SECURITY_BOM_MASK		(U(0xFFF) << 20)
164 #define MC_SECURITY_SIZE_MB_MASK	(U(0x1FFF) << 0)
165 #define MC_SECURITY_BOM_HI_MASK		(U(0x3) << 0)
166 
167 /* Video Memory carveout configuration registers */
168 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
169 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
170 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64C)
171 #define MC_VIDEO_PROTECT_REG_CTRL	U(0x650)
172 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED	U(3)
173 
174 /*
175  * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
176  * non-overlapping Video memory region
177  */
178 #define MC_VIDEO_PROTECT_CLEAR_CFG	U(0x25A0)
179 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO	U(0x25A4)
180 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI	U(0x25A8)
181 #define MC_VIDEO_PROTECT_CLEAR_SIZE	U(0x25AC)
182 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0	U(0x25B0)
183 
184 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
185 #define MC_TZRAM_CARVEOUT_CFG		U(0x2190)
186 #define MC_TZRAM_BASE_LO		U(0x2194)
187 #define MC_TZRAM_BASE_HI		U(0x2198)
188 #define MC_TZRAM_SIZE			U(0x219C)
189 #define MC_TZRAM_CLIENT_ACCESS0_CFG0	U(0x21A0)
190 #define MC_TZRAM_CLIENT_ACCESS1_CFG0	U(0x21A4)
191 #define  TZRAM_ALLOW_MPCORER		(U(1) << 7)
192 #define  TZRAM_ALLOW_MPCOREW		(U(1) << 25)
193 
194 /*******************************************************************************
195  * Tegra UART Controller constants
196  ******************************************************************************/
197 #define TEGRA_UARTA_BASE		U(0x03100000)
198 #define TEGRA_UARTB_BASE		U(0x03110000)
199 #define TEGRA_UARTC_BASE		U(0x0C280000)
200 #define TEGRA_UARTD_BASE		U(0x03130000)
201 #define TEGRA_UARTE_BASE		U(0x03140000)
202 #define TEGRA_UARTF_BASE		U(0x03150000)
203 #define TEGRA_UARTG_BASE		U(0x0C290000)
204 
205 /*******************************************************************************
206  * Tegra Fuse Controller related constants
207  ******************************************************************************/
208 #define TEGRA_FUSE_BASE			U(0x03820000)
209 #define  OPT_SUBREVISION		U(0x248)
210 #define  SUBREVISION_MASK		U(0xFF)
211 
212 /*******************************************************************************
213  * GICv2 & interrupt handling related constants
214  ******************************************************************************/
215 #define TEGRA_GICD_BASE			U(0x03881000)
216 #define TEGRA_GICC_BASE			U(0x03882000)
217 
218 /*******************************************************************************
219  * Security Engine related constants
220  ******************************************************************************/
221 #define TEGRA_SE0_BASE			U(0x03AC0000)
222 #define  SE_MUTEX_WATCHDOG_NS_LIMIT	U(0x6C)
223 #define TEGRA_PKA1_BASE			U(0x03AD0000)
224 #define  PKA_MUTEX_WATCHDOG_NS_LIMIT	U(0x8144)
225 #define TEGRA_RNG1_BASE			U(0x03AE0000)
226 #define  RNG_MUTEX_WATCHDOG_NS_LIMIT	U(0xFE0)
227 
228 /*******************************************************************************
229  * Tegra HSP doorbell #0 constants
230  ******************************************************************************/
231 #define TEGRA_HSP_DBELL_BASE		U(0x03C90000)
232 #define HSP_DBELL_1_ENABLE		U(0x104)
233 #define HSP_DBELL_3_TRIGGER		U(0x300)
234 #define HSP_DBELL_3_ENABLE		U(0x304)
235 
236 /*******************************************************************************
237  * Tegra Clock and Reset Controller constants
238  ******************************************************************************/
239 #define TEGRA_CAR_RESET_BASE		U(0x05000000)
240 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x30)
241 #define TEGRA_GPU_RESET_GPU_SET_OFFSET	U(0x34)
242 #define  GPU_RESET_BIT			(U(1) << 0)
243 #define  GPU_SET_BIT			(U(1) << 0)
244 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET	U(0x6A0004)
245 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET	U(0x6A0008)
246 
247 /*******************************************************************************
248  * Tegra micro-seconds timer constants
249  ******************************************************************************/
250 #define TEGRA_TMRUS_BASE		U(0x0C2E0000)
251 #define TEGRA_TMRUS_SIZE		U(0x1000)
252 
253 /*******************************************************************************
254  * Tegra Power Mgmt Controller constants
255  ******************************************************************************/
256 #define TEGRA_PMC_BASE			U(0x0C360000)
257 
258 /*******************************************************************************
259  * Tegra scratch registers constants
260  ******************************************************************************/
261 #define TEGRA_SCRATCH_BASE		U(0x0C390000)
262 #define  SECURE_SCRATCH_RSV0_HI		U(0x654)
263 #define  SECURE_SCRATCH_RSV1_LO		U(0x658)
264 #define  SECURE_SCRATCH_RSV1_HI		U(0x65C)
265 #define  SECURE_SCRATCH_RSV6		U(0x680)
266 #define  SECURE_SCRATCH_RSV11_LO	U(0x6A8)
267 #define  SECURE_SCRATCH_RSV11_HI	U(0x6AC)
268 #define  SECURE_SCRATCH_RSV53_LO	U(0x7F8)
269 #define  SECURE_SCRATCH_RSV53_HI	U(0x7FC)
270 #define  SECURE_SCRATCH_RSV55_LO	U(0x808)
271 #define  SECURE_SCRATCH_RSV55_HI	U(0x80C)
272 #define  SECURE_SCRATCH_RSV63_LO	U(0x848)
273 #define  SECURE_SCRATCH_RSV63_HI	U(0x84C)
274 #define  SECURE_SCRATCH_RSV64_LO	U(0x850)
275 #define  SECURE_SCRATCH_RSV64_HI	U(0x854)
276 #define  SECURE_SCRATCH_RSV65_LO	U(0x858)
277 #define  SECURE_SCRATCH_RSV65_HI	U(0x85c)
278 #define  SECURE_SCRATCH_RSV66_LO	U(0x860)
279 #define  SECURE_SCRATCH_RSV66_HI	U(0x864)
280 #define  SECURE_SCRATCH_RSV68_LO	U(0x870)
281 
282 #define SCRATCH_RESET_VECTOR_LO		SECURE_SCRATCH_RSV1_LO
283 #define SCRATCH_RESET_VECTOR_HI		SECURE_SCRATCH_RSV1_HI
284 #define SCRATCH_SECURE_BOOTP_FCFG	SECURE_SCRATCH_RSV6
285 #define SCRATCH_MC_TABLE_ADDR_LO	SECURE_SCRATCH_RSV11_LO
286 #define SCRATCH_MC_TABLE_ADDR_HI	SECURE_SCRATCH_RSV11_HI
287 #define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV53_LO
288 #define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV53_HI
289 #define SCRATCH_TZDRAM_ADDR_LO		SECURE_SCRATCH_RSV55_LO
290 #define SCRATCH_TZDRAM_ADDR_HI		SECURE_SCRATCH_RSV55_HI
291 
292 /*******************************************************************************
293  * Tegra Memory Mapped Control Register Access constants
294  ******************************************************************************/
295 #define TEGRA_MMCRAB_BASE		U(0x0E000000)
296 
297 /*******************************************************************************
298  * Tegra Memory Mapped Activity Monitor Register Access constants
299  ******************************************************************************/
300 #define TEGRA_ARM_ACTMON_CTR_BASE	U(0x0E060000)
301 #define TEGRA_DENVER_ACTMON_CTR_BASE	U(0x0E070000)
302 
303 /*******************************************************************************
304  * Tegra SMMU Controller constants
305  ******************************************************************************/
306 #define TEGRA_SMMU0_BASE		U(0x12000000)
307 
308 /*******************************************************************************
309  * Tegra TZRAM constants
310  ******************************************************************************/
311 #define TEGRA_TZRAM_BASE		U(0x30000000)
312 #define TEGRA_TZRAM_SIZE		U(0x40000)
313 
314 /*******************************************************************************
315  * Tegra CCPLEX-BPMP IPC constants
316  ******************************************************************************/
317 #define TEGRA_BPMP_IPC_TX_PHYS_BASE	U(0x3004C000)
318 #define TEGRA_BPMP_IPC_RX_PHYS_BASE	U(0x3004D000)
319 #define TEGRA_BPMP_IPC_CH_MAP_SIZE	U(0x1000) /* 4KB */
320 
321 /*******************************************************************************
322  * Tegra DRAM memory base address
323  ******************************************************************************/
324 #define TEGRA_DRAM_BASE			ULL(0x80000000)
325 #define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
326 
327 #endif /* TEGRA_DEF_H */
328