1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TSPD_PRIVATE_H 8 #define TSPD_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <bl31/interrupt_mgmt.h> 14 #include <context.h> 15 #include <lib/psci/psci.h> 16 17 /******************************************************************************* 18 * Secure Payload PM state information e.g. SP is suspended, uninitialised etc 19 * and macros to access the state information in the per-cpu 'state' flags 20 ******************************************************************************/ 21 #define TSP_PSTATE_OFF 0 22 #define TSP_PSTATE_ON 1 23 #define TSP_PSTATE_SUSPEND 2 24 #define TSP_PSTATE_SHIFT 0 25 #define TSP_PSTATE_MASK 0x3 26 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) 27 #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ 28 << TSP_PSTATE_SHIFT)) 29 #define set_tsp_pstate(st, pst) do { \ 30 clr_tsp_pstate(st); \ 31 st |= (pst & TSP_PSTATE_MASK) << \ 32 TSP_PSTATE_SHIFT; \ 33 } while (0); 34 35 36 /* 37 * This flag is used by the TSPD to determine if the TSP is servicing a yielding 38 * SMC request prior to programming the next entry into the TSP e.g. if TSP 39 * execution is preempted by a non-secure interrupt and handed control to the 40 * normal world. If another request which is distinct from what the TSP was 41 * previously doing arrives, then this flag will be help the TSPD to either 42 * reject the new request or service it while ensuring that the previous context 43 * is not corrupted. 44 */ 45 #define YIELD_SMC_ACTIVE_FLAG_SHIFT 2 46 #define YIELD_SMC_ACTIVE_FLAG_MASK 1 47 #define get_yield_smc_active_flag(state) \ 48 ((state >> YIELD_SMC_ACTIVE_FLAG_SHIFT) \ 49 & YIELD_SMC_ACTIVE_FLAG_MASK) 50 #define set_yield_smc_active_flag(state) (state |= \ 51 1 << YIELD_SMC_ACTIVE_FLAG_SHIFT) 52 #define clr_yield_smc_active_flag(state) (state &= \ 53 ~(YIELD_SMC_ACTIVE_FLAG_MASK \ 54 << YIELD_SMC_ACTIVE_FLAG_SHIFT)) 55 56 /******************************************************************************* 57 * Secure Payload execution state information i.e. aarch32 or aarch64 58 ******************************************************************************/ 59 #define TSP_AARCH32 MODE_RW_32 60 #define TSP_AARCH64 MODE_RW_64 61 62 /******************************************************************************* 63 * The SPD should know the type of Secure Payload. 64 ******************************************************************************/ 65 #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP 66 #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP 67 #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP 68 69 /******************************************************************************* 70 * Secure Payload migrate type information as known to the SPD. We assume that 71 * the SPD is dealing with an MP Secure Payload. 72 ******************************************************************************/ 73 #define TSP_MIGRATE_INFO TSP_TYPE_MP 74 75 /******************************************************************************* 76 * Number of cpus that the present on this platform. TODO: Rely on a topology 77 * tree to determine this in the future to avoid assumptions about mpidr 78 * allocation 79 ******************************************************************************/ 80 #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT 81 82 /******************************************************************************* 83 * Constants that allow assembler code to preserve callee-saved registers of the 84 * C runtime context while performing a security state switch. 85 ******************************************************************************/ 86 #define TSPD_C_RT_CTX_X19 0x0 87 #define TSPD_C_RT_CTX_X20 0x8 88 #define TSPD_C_RT_CTX_X21 0x10 89 #define TSPD_C_RT_CTX_X22 0x18 90 #define TSPD_C_RT_CTX_X23 0x20 91 #define TSPD_C_RT_CTX_X24 0x28 92 #define TSPD_C_RT_CTX_X25 0x30 93 #define TSPD_C_RT_CTX_X26 0x38 94 #define TSPD_C_RT_CTX_X27 0x40 95 #define TSPD_C_RT_CTX_X28 0x48 96 #define TSPD_C_RT_CTX_X29 0x50 97 #define TSPD_C_RT_CTX_X30 0x58 98 #define TSPD_C_RT_CTX_SIZE 0x60 99 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) 100 101 /******************************************************************************* 102 * Constants that allow assembler code to preserve caller-saved registers of the 103 * SP context while performing a TSP preemption. 104 * Note: These offsets have to match with the offsets for the corresponding 105 * registers in cpu_context as we are using memcpy to copy the values from 106 * cpu_context to sp_ctx. 107 ******************************************************************************/ 108 #define TSPD_SP_CTX_X0 0x0 109 #define TSPD_SP_CTX_X1 0x8 110 #define TSPD_SP_CTX_X2 0x10 111 #define TSPD_SP_CTX_X3 0x18 112 #define TSPD_SP_CTX_X4 0x20 113 #define TSPD_SP_CTX_X5 0x28 114 #define TSPD_SP_CTX_X6 0x30 115 #define TSPD_SP_CTX_X7 0x38 116 #define TSPD_SP_CTX_X8 0x40 117 #define TSPD_SP_CTX_X9 0x48 118 #define TSPD_SP_CTX_X10 0x50 119 #define TSPD_SP_CTX_X11 0x58 120 #define TSPD_SP_CTX_X12 0x60 121 #define TSPD_SP_CTX_X13 0x68 122 #define TSPD_SP_CTX_X14 0x70 123 #define TSPD_SP_CTX_X15 0x78 124 #define TSPD_SP_CTX_X16 0x80 125 #define TSPD_SP_CTX_X17 0x88 126 #define TSPD_SP_CTX_SIZE 0x90 127 #define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) 128 129 #ifndef __ASSEMBLER__ 130 131 #include <stdint.h> 132 133 #include <lib/cassert.h> 134 135 /* 136 * The number of arguments to save during a SMC call for TSP. 137 * Currently only x1 and x2 are used by TSP. 138 */ 139 #define TSP_NUM_ARGS 0x2 140 141 /* AArch64 callee saved general purpose register context structure. */ 142 DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); 143 144 /* 145 * Compile time assertion to ensure that both the compiler and linker 146 * have the same double word aligned view of the size of the C runtime 147 * register context. 148 */ 149 CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 150 assert_spd_c_rt_regs_size_mismatch); 151 152 /* SEL1 Secure payload (SP) caller saved register context structure. */ 153 DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); 154 155 /* 156 * Compile time assertion to ensure that both the compiler and linker 157 * have the same double word aligned view of the size of the C runtime 158 * register context. 159 */ 160 CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ 161 assert_spd_sp_regs_size_mismatch); 162 163 /******************************************************************************* 164 * Structure which helps the SPD to maintain the per-cpu state of the SP. 165 * 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when 166 * the TSP has been preempted. 167 * 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when 168 * the TSP has been preempted. 169 * 'state' - collection of flags to track SP state e.g. on/off 170 * 'mpidr' - mpidr to associate a context with a cpu 171 * 'c_rt_ctx' - stack address to restore C runtime context from after 172 * returning from a synchronous entry into the SP. 173 * 'cpu_ctx' - space to maintain SP architectural state 174 * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 175 * which will queried using the TSP_GET_ARGS SMC by TSP. 176 * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved 177 * register context after it has been preempted by an EL3 178 * routed NS interrupt and when a Secure Interrupt is taken 179 * to SP. 180 ******************************************************************************/ 181 typedef struct tsp_context { 182 uint64_t saved_elr_el3; 183 uint32_t saved_spsr_el3; 184 uint32_t state; 185 uint64_t mpidr; 186 uint64_t c_rt_ctx; 187 cpu_context_t cpu_ctx; 188 uint64_t saved_tsp_args[TSP_NUM_ARGS]; 189 #if TSP_NS_INTR_ASYNC_PREEMPT 190 sp_ctx_regs_t sp_ctx; 191 bool preempted_by_sel1_intr; 192 #endif 193 } tsp_context_t; 194 195 /* Helper macros to store and retrieve tsp args from tsp_context */ 196 #define store_tsp_args(_tsp_ctx, _x1, _x2) do {\ 197 _tsp_ctx->saved_tsp_args[0] = _x1;\ 198 _tsp_ctx->saved_tsp_args[1] = _x2;\ 199 } while (0) 200 201 #define get_tsp_args(_tsp_ctx, _x1, _x2) do {\ 202 _x1 = _tsp_ctx->saved_tsp_args[0];\ 203 _x2 = _tsp_ctx->saved_tsp_args[1];\ 204 } while (0) 205 206 /* TSPD power management handlers */ 207 extern const spd_pm_ops_t tspd_pm; 208 209 /******************************************************************************* 210 * Forward declarations 211 ******************************************************************************/ 212 typedef struct tsp_vectors tsp_vectors_t; 213 214 /******************************************************************************* 215 * Function & Data prototypes 216 ******************************************************************************/ 217 uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); 218 void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 219 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); 220 void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); 221 void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, 222 uint32_t rw, 223 uint64_t pc, 224 tsp_context_t *tsp_ctx); 225 int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx); 226 227 uint64_t tspd_handle_sp_preemption(void *handle); 228 229 extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 230 extern tsp_vectors_t *tsp_vectors; 231 #endif /*__ASSEMBLER__*/ 232 233 #endif /* TSPD_PRIVATE_H */ 234