1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOC_TZASC_H 8 #define SOC_TZASC_H 9 10 #define MAX_NUM_TZC_REGION 3 11 12 /* TZASC related constants */ 13 #define TZASC_CONFIGURATION_REG 0x000 14 #define TZASC_SECURITY_INV_REG 0x034 15 #define TZASC_SECURITY_INV_EN 0x1 16 #define TZASC_REGIONS_REG 0x100 17 /* As region address should address atleast 32KB memory. */ 18 #define TZASC_REGION_LOWADDR_MASK 0xFFFF8000 19 #define TZASC_REGION_LOWADDR_OFFSET 0x0 20 #define TZASC_REGION_HIGHADDR_OFFSET 0x4 21 #define TZASC_REGION_ATTR_OFFSET 0x8 22 #define TZASC_REGION_ENABLED 1 23 #define TZASC_REGION_DISABLED 0 24 #define TZASC_REGION_SIZE_32KB 0xE 25 #define TZASC_REGION_SIZE_64KB 0xF 26 #define TZASC_REGION_SIZE_128KB 0x10 27 #define TZASC_REGION_SIZE_256KB 0x11 28 #define TZASC_REGION_SIZE_512KB 0x12 29 #define TZASC_REGION_SIZE_1MB 0x13 30 #define TZASC_REGION_SIZE_2MB 0x14 31 #define TZASC_REGION_SIZE_4MB 0x15 32 #define TZASC_REGION_SIZE_8MB 0x16 33 #define TZASC_REGION_SIZE_16MB 0x17 34 #define TZASC_REGION_SIZE_32MB 0x18 35 #define TZASC_REGION_SIZE_64MB 0x19 36 #define TZASC_REGION_SIZE_128MB 0x1A 37 #define TZASC_REGION_SIZE_256MB 0x1B 38 #define TZASC_REGION_SIZE_512MB 0x1C 39 #define TZASC_REGION_SIZE_1GB 0x1D 40 #define TZASC_REGION_SIZE_2GB 0x1E 41 #define TZASC_REGION_SIZE_4GB 0x1F 42 #define TZASC_REGION_SIZE_8GB 0x20 43 #define TZASC_REGION_SIZE_16GB 0x21 44 #define TZASC_REGION_SIZE_32GB 0x22 45 #define TZASC_REGION_SECURITY_SR (1 << 3) 46 #define TZASC_REGION_SECURITY_SW (1 << 2) 47 #define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR| \ 48 TZASC_REGION_SECURITY_SW) 49 #define TZASC_REGION_SECURITY_NSR (1 << 1) 50 #define TZASC_REGION_SECURITY_NSW 1 51 #define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR| \ 52 TZASC_REGION_SECURITY_NSW) 53 54 #define CSU_SEC_ACCESS_REG_OFFSET 0x21C 55 #define TZASC_BYPASS_MUX_DISABLE 0x4 56 #define CCI_TERMINATE_BARRIER_TX 0x8 57 #define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000 58 59 struct tzc380_reg { 60 unsigned int secure; 61 unsigned int enabled; 62 unsigned int low_addr; 63 unsigned int high_addr; 64 unsigned int size; 65 unsigned int sub_mask; 66 }; 67 68 /* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */ 69 70 static const struct tzc380_reg tzc380_reg_list[] = { 71 { 72 TZASC_REGION_SECURITY_NSRW, /* .secure attr */ 73 0x0, /* .enabled */ 74 0x0, /* .lowaddr */ 75 0x0, /* .highaddr */ 76 0x0, /* .size */ 77 0x0, /* .submask */ 78 }, 79 { 80 TZASC_REGION_SECURITY_SRW, 81 TZASC_REGION_ENABLED, 82 0xFC000000, 83 0x0, 84 TZASC_REGION_SIZE_64MB, 85 0x80, /* Disable region 7 */ 86 }, 87 /* reserve 2M non-scure memory for OPTEE public memory */ 88 { 89 TZASC_REGION_SECURITY_SRW, 90 TZASC_REGION_ENABLED, 91 0xFF800000, 92 0x0, 93 TZASC_REGION_SIZE_8MB, 94 0xC0, /* Disable region 6 & 7 */ 95 }, 96 97 {} 98 }; 99 100 #endif /* SOC_TZASC_H */ 101