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Searched refs:ULL (Results 1 – 25 of 134) sorted by relevance

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/trusted-firmware-a/include/arch/aarch64/
A Darch.h42 #define MPIDR_AFFLVL0 ULL(0x0)
43 #define MPIDR_AFFLVL1 ULL(0x1)
44 #define MPIDR_AFFLVL2 ULL(0x2)
45 #define MPIDR_AFFLVL3 ULL(0x3)
192 #define EL_IMPL_NONE ULL(0)
666 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
667 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
672 #define TCR_TxSZ_MIN ULL(16)
723 #define TCR_TG0_MASK ULL(3)
729 #define TCR_TG1_MASK ULL(3)
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/trusted-firmware-a/plat/rpi/rpi3/include/
A Drpi_hw.h16 #define RPI_IO_BASE ULL(0x3F000000)
17 #define RPI_IO_SIZE ULL(0x01000000)
22 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
25 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
26 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
27 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
43 #define RPI3_IO_PM_OFFSET ULL(0x00100000)
46 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
47 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
48 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
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A Dplatform_def.h20 #define PLATFORM_STACK_SIZE ULL(0x1000)
67 #define SEC_ROM_BASE ULL(0x00000000)
68 #define SEC_ROM_SIZE ULL(0x00010000)
75 #define SEC_SRAM_BASE ULL(0x00200000)
76 #define SEC_SRAM_SIZE ULL(0x00100000)
82 #define NS_DRAM0_BASE ULL(0x00400000)
83 #define NS_DRAM0_SIZE ULL(0x00C00000)
85 #define SEC_ROM_BASE ULL(0x00000000)
86 #define SEC_ROM_SIZE ULL(0x00020000)
93 #define SEC_SRAM_BASE ULL(0x10000000)
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/trusted-firmware-a/plat/rpi/rpi4/include/
A Drpi_hw.h16 #define RPI_IO_BASE ULL(0xFC000000)
17 #define RPI_IO_SIZE ULL(0x04000000)
24 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
27 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
28 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
45 #define RPI3_IO_PM_OFFSET ULL(0x00100000)
48 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
49 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
50 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
66 #define RPI3_IO_RNG_OFFSET ULL(0x00104000)
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A Dplatform_def.h20 #define PLATFORM_STACK_SIZE ULL(0x1000)
82 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
87 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
94 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
95 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
96 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
104 #define PLAT_MAX_BL31_SIZE ULL(0x80000)
106 #define BL31_BASE ULL(0x1000)
107 #define BL31_LIMIT ULL(0x80000)
108 #define BL31_PROGBITS_LIMIT ULL(0x80000)
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/trusted-firmware-a/include/lib/cpus/aarch64/
A Dcortex_a72.h20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
36 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
49 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)
51 #define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8)
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A Dcortex_a57.h30 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
31 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
32 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
33 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
52 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
53 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
54 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
57 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
58 #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
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A Dneoverse_n1.h36 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
38 #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
45 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
46 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
50 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
51 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
52 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
55 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
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A Drainier.h36 #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
37 #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
44 #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
45 #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
49 #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
50 #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
51 #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
52 #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
53 #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
54 #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
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A Dneoverse_n2.h17 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
23 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
24 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
30 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
31 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
37 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
43 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
44 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
45 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
51 #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
A Dcortex_a76.h21 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
22 #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
29 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
31 #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
35 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
37 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
41 #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
A Dcortex_a53.h29 #define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
48 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
50 #define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
52 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
54 #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
A Dneoverse_v1.h16 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
17 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
18 #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
32 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
33 #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
A Dcortex_a55.h21 #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)
28 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)
29 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
30 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)
37 #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
A Dcortex_a78.h18 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
19 #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
32 #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
35 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
36 #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
A Dcortex_a710.h16 #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
28 #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
34 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
40 #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
/trusted-firmware-a/include/lib/cpus/aarch32/
A Dcortex_a57.h29 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
30 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
31 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
32 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
47 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
50 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
51 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
52 #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
53 #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
56 #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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A Dcortex_a72.h20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
36 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
/trusted-firmware-a/include/lib/xlat_tables/
A Dxlat_tables_defs.h52 #define XN (ULL(1) << 2)
54 #define UXN (ULL(1) << 2)
55 #define PXN (ULL(1) << 1)
56 #define CONT_HINT (ULL(1) << 0)
67 #define GP (ULL(1) << 50)
127 #define AP2_RO ULL(0x1)
128 #define AP2_RW ULL(0x0)
131 #define AP1_ACCESS_UNPRIVILEGED ULL(0x1)
133 #define AP1_RES1 ULL(0x1)
146 #define ATTR_NON_CACHEABLE_INDEX ULL(0x2)
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/trusted-firmware-a/plat/arm/board/morello/include/
A Dplatform_def.h15 #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000)
18 #define PLAT_ARM_RUN_UART_BASE ULL(0x2A410000)
24 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
25 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
36 #define MORELLO_SCMI_PAYLOAD_BASE ULL(0x45400000)
38 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE ULL(0x45400000)
78 #define MORELLO_DEVICE_BASE ULL(0x08000000)
79 #define MORELLO_DEVICE_SIZE ULL(0x48000000)
/trusted-firmware-a/include/bl32/payloads/
A Dtlk.h39 #define TLK_REQUEST_DONE (0x32000001 | (ULL(1) << 31))
40 #define TLK_PREEMPTED (0x32000002 | (ULL(1) << 31))
41 #define TLK_ENTRY_DONE (0x32000003 | (ULL(1) << 31))
42 #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))
43 #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))
44 #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))
45 #define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31))
/trusted-firmware-a/plat/socionext/synquacer/include/
A Dplatform_def.h97 #define PLAT_SPM_BUF_SIZE ULL(0x10000)
105 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000)
112 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000)
116 #define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000)
123 #define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000)
134 #define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000)
138 #define PLAT_SPM_COOKIE_0 ULL(0)
139 #define PLAT_SPM_COOKIE_1 ULL(0)
150 #define PLAT_SQ_UART1_SIZE ULL(0x1000)
157 #define PLAT_SQ_PERIPH_SIZE ULL(0x8000000)
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/trusted-firmware-a/include/lib/xlat_tables/aarch64/
A Dxlat_tables_aarch64.h57 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MAX))
61 (ULL(1) << (U(64) - TCR_TxSZ_MAX_TTST))
62 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MIN))
89 (((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
91 : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
93 : (((_virt_addr_space_sz) > (ULL(1) << L2_XLAT_ADDRESS_SHIFT)) \
/trusted-firmware-a/include/plat/arm/common/
A Darm_spm_def.h20 #define ARM_SP_IMAGE_SIZE ULL(0x300000)
46 #define PLAT_SPM_BUF_SIZE ULL(0x100000)
65 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
80 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
100 #define PLAT_SPM_COOKIE_0 ULL(0)
101 #define PLAT_SPM_COOKIE_1 ULL(0)
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/include/
A Dmce_private.h18 #define CLUSTER_CSTATE_MASK ULL(0x7)
20 #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7)
21 #define CCPLEX_CSTATE_MASK ULL(0x3)
22 #define CCPLEX_CSTATE_SHIFT ULL(8)
23 #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15)
24 #define SYSTEM_CSTATE_MASK ULL(0xF)
25 #define SYSTEM_CSTATE_SHIFT ULL(16)
26 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22)
28 #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23)
30 #define CSTATE_WAKE_MASK_SHIFT ULL(32)
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