1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCE_PRIVATE_H 8 #define MCE_PRIVATE_H 9 10 #include <lib/mmio.h> 11 12 #include <tegra_def.h> 13 14 /******************************************************************************* 15 * Macros to prepare CSTATE info request 16 ******************************************************************************/ 17 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 18 #define CLUSTER_CSTATE_MASK ULL(0x7) 19 #define CLUSTER_CSTATE_SHIFT U(0) 20 #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7) 21 #define CCPLEX_CSTATE_MASK ULL(0x3) 22 #define CCPLEX_CSTATE_SHIFT ULL(8) 23 #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15) 24 #define SYSTEM_CSTATE_MASK ULL(0xF) 25 #define SYSTEM_CSTATE_SHIFT ULL(16) 26 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22) 27 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22) 28 #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23) 29 #define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31) 30 #define CSTATE_WAKE_MASK_SHIFT ULL(32) 31 #define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF) 32 33 /******************************************************************************* 34 * Auto-CC3 control macros 35 ******************************************************************************/ 36 #define MCE_AUTO_CC3_FREQ_MASK U(0x1FF) 37 #define MCE_AUTO_CC3_FREQ_SHIFT U(0) 38 #define MCE_AUTO_CC3_VTG_MASK U(0x7F) 39 #define MCE_AUTO_CC3_VTG_SHIFT U(16) 40 #define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31) 41 42 /******************************************************************************* 43 * Macros for the 'IS_SC7_ALLOWED' command 44 ******************************************************************************/ 45 #define MCE_SC7_ALLOWED_MASK U(0x7) 46 #define MCE_SC7_WAKE_TIME_SHIFT U(32) 47 48 /******************************************************************************* 49 * Macros for 'read/write ctats' commands 50 ******************************************************************************/ 51 #define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32) 52 #define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF) 53 54 /******************************************************************************* 55 * Macros for 'update crossover threshold' command 56 ******************************************************************************/ 57 #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32) 58 59 /******************************************************************************* 60 * MCA argument macros 61 ******************************************************************************/ 62 #define MCA_ARG_ERROR_MASK U(0xFF) 63 #define MCA_ARG_FINISH_SHIFT U(24) 64 #define MCA_ARG_FINISH_MASK U(0xFF) 65 66 /******************************************************************************* 67 * Uncore PERFMON ARI macros 68 ******************************************************************************/ 69 #define UNCORE_PERFMON_CMD_READ U(0) 70 #define UNCORE_PERFMON_CMD_WRITE U(1) 71 72 #define UNCORE_PERFMON_CMD_MASK U(0xFF) 73 #define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF) 74 #define UNCORE_PERFMON_SELECTOR_MASK U(0xF) 75 #define UNCORE_PERFMON_REG_MASK U(0xFF) 76 #define UNCORE_PERFMON_CTR_MASK U(0xFF) 77 #define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF) 78 79 /******************************************************************************* 80 * Structure populated by arch specific code to export routines which perform 81 * common low level MCE functions 82 ******************************************************************************/ 83 typedef struct arch_mce_ops { 84 /* 85 * This ARI request sets up the MCE to start execution on assertion 86 * of STANDBYWFI, update the core power state and expected wake time, 87 * then determine the proper power state to enter. 88 */ 89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state, 90 uint32_t wake_time); 91 /* 92 * This ARI request allows updating of the CLUSTER_CSTATE, 93 * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. 94 */ 95 int32_t (*update_cstate_info)(uint32_t ari_base, 96 uint32_t cluster, 97 uint32_t ccplex, 98 uint32_t system, 99 uint8_t sys_state_force, 100 uint32_t wake_mask, 101 uint8_t update_wake_mask); 102 /* 103 * This ARI request allows updating of power state crossover 104 * threshold times. An index value specifies which crossover 105 * state is being updated. 106 */ 107 int32_t (*update_crossover_time)(uint32_t ari_base, 108 uint32_t type, 109 uint32_t time); 110 /* 111 * This ARI request allows read access to statistical information 112 * related to power states. 113 */ 114 uint64_t (*read_cstate_stats)(uint32_t ari_base, 115 uint32_t state); 116 /* 117 * This ARI request allows write access to statistical information 118 * related to power states. 119 */ 120 int32_t (*write_cstate_stats)(uint32_t ari_base, 121 uint32_t state, 122 uint32_t stats); 123 /* 124 * This ARI request allows the CPU to understand the features 125 * supported by the MCE firmware. 126 */ 127 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, 128 uint32_t data); 129 /* 130 * This ARI request allows querying the CCPLEX to determine if 131 * the CCx state is allowed given a target core C-state and wake 132 * time. If the CCx state is allowed, the response indicates CCx 133 * must be entered. If the CCx state is not allowed, the response 134 * indicates CC6/CC7 can't be entered 135 */ 136 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, 137 uint32_t wake_time); 138 /* 139 * This ARI request allows querying the CCPLEX to determine if 140 * the SC7 state is allowed given a target core C-state and wake 141 * time. If the SC7 state is allowed, all cores but the associated 142 * core are offlined (WAKE_EVENTS are set to 0) and the response 143 * indicates SC7 must be entered. If the SC7 state is not allowed, 144 * the response indicates SC7 can't be entered 145 */ 146 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, 147 uint32_t wake_time); 148 /* 149 * This ARI request allows a core to bring another offlined core 150 * back online to the C0 state. Note that a core is offlined by 151 * entering a C-state where the WAKE_MASK is all 0. 152 */ 153 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid); 154 /* 155 * This ARI request allows the CPU to enable/disable Auto-CC3 idle 156 * state. 157 */ 158 int32_t (*cc3_ctrl)(uint32_t ari_base, 159 uint32_t freq, 160 uint32_t volt, 161 uint8_t enable); 162 /* 163 * This ARI request allows updating the reset vector register for 164 * D15 and A57 CPUs. 165 */ 166 int32_t (*update_reset_vector)(uint32_t ari_base); 167 /* 168 * This ARI request instructs the ROC to flush A57 data caches in 169 * order to maintain coherency with the Denver cluster. 170 */ 171 int32_t (*roc_flush_cache)(uint32_t ari_base); 172 /* 173 * This ARI request instructs the ROC to flush A57 data caches along 174 * with the caches covering ARM code in order to maintain coherency 175 * with the Denver cluster. 176 */ 177 int32_t (*roc_flush_cache_trbits)(uint32_t ari_base); 178 /* 179 * This ARI request instructs the ROC to clean A57 data caches along 180 * with the caches covering ARM code in order to maintain coherency 181 * with the Denver cluster. 182 */ 183 int32_t (*roc_clean_cache)(uint32_t ari_base); 184 /* 185 * This ARI request reads/writes the Machine Check Arch. (MCA) 186 * registers. 187 */ 188 uint64_t (*read_write_mca)(uint32_t ari_base, 189 uint64_t cmd, 190 uint64_t *data); 191 /* 192 * Some MC GSC (General Security Carveout) register values are 193 * expected to be changed by TrustZone secure ARM code after boot. 194 * Since there is no hardware mechanism for the CCPLEX to know 195 * that an MC GSC register has changed to allow it to update its 196 * own internal GSC register, there needs to be a mechanism that 197 * can be used by ARM code to cause the CCPLEX to update its GSC 198 * register value. This ARI request allows updating the GSC register 199 * value for a certain carveout in the CCPLEX. 200 */ 201 int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); 202 /* 203 * This ARI request instructs the CCPLEX to either shutdown or 204 * reset the entire system 205 */ 206 void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); 207 /* 208 * This ARI request reads/writes data from/to Uncore PERFMON 209 * registers 210 */ 211 int32_t (*read_write_uncore_perfmon)(uint32_t ari_base, 212 uint64_t req, uint64_t *data); 213 /* 214 * This ARI implements ARI_MISC_CCPLEX commands. This can be 215 * used to enable/disable coresight clock gating. 216 */ 217 void (*misc_ccplex)(uint32_t ari_base, uint32_t index, 218 uint32_t value); 219 } arch_mce_ops_t; 220 221 /* declarations for ARI/NVG handler functions */ 222 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 223 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 224 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 225 uint8_t update_wake_mask); 226 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 227 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); 228 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 229 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); 230 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 231 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 232 int32_t ari_online_core(uint32_t ari_base, uint32_t core); 233 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 234 int32_t ari_reset_vector_update(uint32_t ari_base); 235 int32_t ari_roc_flush_cache_trbits(uint32_t ari_base); 236 int32_t ari_roc_flush_cache(uint32_t ari_base); 237 int32_t ari_roc_clean_cache(uint32_t ari_base); 238 uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data); 239 int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); 240 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); 241 int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, 242 uint64_t req, uint64_t *data); 243 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); 244 245 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 246 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 247 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 248 uint8_t update_wake_mask); 249 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 250 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); 251 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 252 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 253 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 254 int32_t nvg_online_core(uint32_t ari_base, uint32_t core); 255 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 256 257 extern void nvg_set_request_data(uint64_t req, uint64_t data); 258 extern void nvg_set_request(uint64_t req); 259 extern uint64_t nvg_get_result(void); 260 #endif /* MCE_PRIVATE_H */ 261