1 /* 2 * Copyright (c) 2017 - 2021, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef USB_PHY_H 8 #define USB_PHY_H 9 10 #include <stdint.h> 11 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 16 #include <platform_def.h> 17 18 #define DRDU2_U2PLL_NDIV_FRAC_OFFSET 0x0U 19 20 #define DRDU2_U2PLL_NDIV_INT 0x4U 21 22 #define DRDU2_U2PLL_CTRL 0x8U 23 #define DRDU2_U2PLL_LOCK BIT(6U) 24 #define DRDU2_U2PLL_RESETB BIT(5U) 25 #define DRDU2_U2PLL_PDIV_MASK 0xFU 26 #define DRDU2_U2PLL_PDIV_OFFSET 1U 27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U) 28 29 #define DRDU2_PHY_CTRL 0x0CU 30 #define DRDU2_U2IDDQ BIT(30U) 31 #define DRDU2_U2SOFT_RST_N BIT(29U) 32 #define DRDU2_U2PHY_ON_FLAG BIT(22U) 33 #define DRDU2_U2PHY_PCTL_MASK 0xFFFFU 34 #define DRDU2_U2PHY_PCTL_OFFSET 6U 35 #define DRDU2_U2PHY_RESETB BIT(5U) 36 #define DRDU2_U2PHY_ISO BIT(4U) 37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U) 38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U) 39 #define DRDU2_U2AFE_LDO_PWRDWNB BIT(1U) 40 #define DRDU2_U2CTRL_CORERDY BIT(0U) 41 42 #define DRDU2_STRAP_CTRL 0x18U 43 #define DRDU2_FORCE_HOST_MODE BIT(5U) 44 #define DRDU2_FORCE_DEVICE_MODE BIT(4U) 45 #define BDC_USB_STP_SPD_MASK 0x7U 46 #define BDC_USB_STP_SPD_OFFSET 0U 47 48 #define DRDU2_PWR_CTRL 0x1CU 49 #define DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I BIT(2U) 50 #define DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I BIT(1U) 51 52 #define DRDU2_SOFT_RESET_CTRL 0x20U 53 #define DRDU2_BDC_AXI_SOFT_RST_N BIT(0U) 54 55 #define USB3H_U2PLL_NDIV_FRAC 0x4U 56 57 #define USB3H_U2PLL_NDIV_INT 0x8U 58 59 #define USB3H_U2PLL_CTRL 0xCU 60 #define USB3H_U2PLL_LOCK BIT(6U) 61 #define USB3H_U2PLL_RESETB BIT(5U) 62 #define USB3H_U2PLL_PDIV_MASK 0xFU 63 #define USB3H_U2PLL_PDIV_OFFSET 1U 64 65 #define USB3H_U2PHY_CTRL 0x10U 66 #define USB3H_U2PHY_ON_FLAG 22U 67 #define USB3H_U2PHY_PCTL_MASK 0xFFFFU 68 #define USB3H_U2PHY_PCTL_OFFSET 6U 69 #define USB3H_U2PHY_IDDQ BIT(29U) 70 #define USB3H_U2PHY_RESETB BIT(5U) 71 #define USB3H_U2PHY_ISO BIT(4U) 72 #define USB3H_U2AFE_BG_PWRDWNB BIT(3U) 73 #define USB3H_U2AFE_PLL_PWRDWNB BIT(2U) 74 #define USB3H_U2AFE_LDO_PWRDWNB BIT(1U) 75 #define USB3H_U2CTRL_CORERDY BIT(0U) 76 77 #define USB3H_U3PHY_CTRL 0x14U 78 #define USB3H_U3SOFT_RST_N BIT(30U) 79 #define USB3H_U3MDIO_RESETB_I BIT(29U) 80 #define USB3H_U3POR_RESET_I BIT(28U) 81 #define USB3H_U3PHY_PCTL_MASK 0xFFFFU 82 #define USB3H_U3PHY_PCTL_OFFSET 2U 83 #define USB3H_U3PHY_RESETB BIT(1U) 84 85 #define USB3H_U3PHY_PLL_CTRL 0x18U 86 #define USB3H_U3PLL_REFCLK_MASK 0x7U 87 #define USB3H_U3PLL_REFCLK_OFFSET 4U 88 #define USB3H_U3PLL_SS_LOCK BIT(3U) 89 #define USB3H_U3PLL_SEQ_START BIT(2U) 90 #define USB3H_U3SSPLL_SUSPEND_EN BIT(1U) 91 #define USB3H_U3PLL_RESETB BIT(0U) 92 93 #define USB3H_PWR_CTRL 0x28U 94 #define USB3H_PWR_CTRL_OVERRIDE_I_R 4U 95 #define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN BIT(11U) 96 #define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN BIT(10U) 97 98 #define USB3H_SOFT_RESET_CTRL 0x2CU 99 #define USB3H_XHC_AXI_SOFT_RST_N BIT(1U) 100 101 #define USB3H_PHY_PWR_CTRL 0x38U 102 #define USB3H_DISABLE_USB30_P0 BIT(2U) 103 #define USB3H_DISABLE_EUSB_P1 BIT(1U) 104 #define USB3H_DISABLE_EUSB_P0 BIT(0U) 105 106 107 #define DRDU3_U2PLL_NDIV_FRAC 0x4U 108 109 #define DRDU3_U2PLL_NDIV_INT 0x8U 110 111 #define DRDU3_U2PLL_CTRL 0xCU 112 #define DRDU3_U2PLL_LOCK BIT(6U) 113 #define DRDU3_U2PLL_RESETB BIT(5U) 114 #define DRDU3_U2PLL_PDIV_MASK 0xFU 115 #define DRDU3_U2PLL_PDIV_OFFSET 1U 116 117 #define DRDU3_U2PHY_CTRL 0x10U 118 #define DRDU3_U2PHY_IDDQ BIT(29U) 119 #define DRDU3_U2PHY_ON_FLAG BIT(22U) 120 #define DRDU3_U2PHY_PCTL_MASK 0xFFFFU 121 #define DRDU3_U2PHY_PCTL_OFFSET 6U 122 #define DRDU3_U2PHY_RESETB BIT(5U) 123 #define DRDU3_U2PHY_ISO BIT(4U) 124 #define DRDU3_U2AFE_BG_PWRDWNB BIT(3U) 125 #define DRDU3_U2AFE_PLL_PWRDWNB BIT(2U) 126 #define DRDU3_U2AFE_LDO_PWRDWNB BIT(1U) 127 #define DRDU3_U2CTRL_CORERDY BIT(0U) 128 129 #define DRDU3_U3PHY_CTRL 0x14U 130 #define DRDU3_U3XHC_SOFT_RST_N BIT(31U) 131 #define DRDU3_U3BDC_SOFT_RST_N BIT(30U) 132 #define DRDU3_U3MDIO_RESETB_I BIT(29U) 133 #define DRDU3_U3POR_RESET_I BIT(28U) 134 #define DRDU3_U3PHY_PCTL_MASK 0xFFFFU 135 #define DRDU3_U3PHY_PCTL_OFFSET 2U 136 #define DRDU3_U3PHY_RESETB BIT(1U) 137 138 #define DRDU3_U3PHY_PLL_CTRL 0x18U 139 #define DRDU3_U3PLL_REFCLK_MASK 0x7U 140 #define DRDU3_U3PLL_REFCLK_OFFSET 4U 141 #define DRDU3_U3PLL_SS_LOCK BIT(3U) 142 #define DRDU3_U3PLL_SEQ_START BIT(2U) 143 #define DRDU3_U3SSPLL_SUSPEND_EN BIT(1U) 144 #define DRDU3_U3PLL_RESETB BIT(0U) 145 146 #define DRDU3_STRAP_CTRL 0x28U 147 #define BDC_USB_STP_SPD_MASK 0x7U 148 #define BDC_USB_STP_SPD_OFFSET 0U 149 #define BDC_USB_STP_SPD_SS 0x0U 150 #define BDC_USB_STP_SPD_HS 0x2U 151 152 #define DRDU3_PWR_CTRL 0x2cU 153 #define DRDU3_U2PHY_DFE_SWITCH_PWROKIN BIT(12U) 154 #define DRDU3_U2PHY_DFE_SWITCH_PWRONIN BIT(11U) 155 #define DRDU3_PWR_CTRL_OVERRIDE_I_R 4U 156 157 #define DRDU3_SOFT_RESET_CTRL 0x30U 158 #define DRDU3_XHC_AXI_SOFT_RST_N BIT(1U) 159 #define DRDU3_BDC_AXI_SOFT_RST_N BIT(0U) 160 161 #define DRDU3_PHY_PWR_CTRL 0x3cU 162 #define DRDU3_DISABLE_USB30_P0 BIT(2U) 163 #define DRDU3_DISABLE_EUSB_P1 BIT(1U) 164 #define DRDU3_DISABLE_EUSB_P0 BIT(0U) 165 166 #define PLL_REFCLK_PAD 0x0U 167 #define PLL_REFCLK_25MHZ 0x1U 168 #define PLL_REFCLK_96MHZ 0x2U 169 #define PLL_REFCLK_INTERNAL 0x3U 170 /* USB PLL lock time out for 10 ms */ 171 #define PLL_LOCK_RETRY_COUNT 10000U 172 173 174 #define U2PLL_NDIV_INT_VAL 0x13U 175 #define U2PLL_NDIV_FRAC_VAL 0x1005U 176 #define U2PLL_PDIV_VAL 0x1U 177 /* 178 * Using external FSM 179 * BIT-3:2: device mode; mode is not effect 180 * BIT-1: soft reset active low 181 */ 182 #define U2PHY_PCTL_VAL 0x0003U 183 /* Non-driving signal low */ 184 #define U2PHY_PCTL_NON_DRV_LOW 0x0002U 185 #define U3PHY_PCTL_VAL 0x0006U 186 187 #define MAX_NR_PORTS 3U 188 189 #define USB3H_DRDU2_PHY 1U 190 #define DRDU3_PHY 2U 191 192 #define USB_HOST_MODE 1U 193 #define USB_DEV_MODE 2U 194 195 #define USB3SS_PORT 0U 196 #define DRDU2_PORT 1U 197 #define USB3HS_PORT 2U 198 199 #define DRD3SS_PORT 0U 200 #define DRD3HS_PORT 1U 201 202 #define SR_USB_PHY_COUNT 2U 203 204 #define DRDU3_PIPE_CTRL 0x68500000U 205 #define DRDU3H_XHC_REGS_CPLIVER 0x68501000U 206 #define USB3H_PIPE_CTRL 0x68510000U 207 #define DRD2U3H_XHC_REGS_CPLIVER 0x68511000U 208 #define DRDU2_U2PLL_NDIV_FRAC 0x68520000U 209 210 #define AXI_DEBUG_CTRL 0x68500038U 211 #define AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(12U) 212 213 #define USB3H_DEBUG_CTRL 0x68510034U 214 #define USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(7U) 215 216 typedef struct _usb_phy_port usb_phy_port_t; 217 218 typedef struct { 219 uint32_t drdu2reg; 220 uint32_t usb3hreg; 221 uint32_t drdu3reg; 222 uint32_t phy_id; 223 uint32_t ports_enabled; 224 uint32_t initialized; 225 usb_phy_port_t *phy_port; 226 } usb_phy_t; 227 228 struct _usb_phy_port { 229 uint32_t port_id; 230 uint32_t mode; 231 uint32_t enabled; 232 usb_phy_t *p; 233 }; 234 235 struct u2_phy_ext_fsm { 236 uint32_t pll_ctrl_reg; 237 uint32_t phy_ctrl_reg; 238 uint32_t phy_iddq; 239 uint32_t pwr_ctrl_reg; 240 uint32_t pwr_okin; 241 uint32_t pwr_onin; 242 }; 243 244 #endif /* USB_PHY_H */ 245