1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef V2M_DEF_H 7 #define V2M_DEF_H 8 9 #include <lib/utils_def.h> 10 11 /* Base address of all V2M */ 12 #ifdef PLAT_V2M_OFFSET 13 #define V2M_OFFSET PLAT_V2M_OFFSET 14 #else 15 #define V2M_OFFSET UL(0) 16 #endif 17 18 /* V2M motherboard system registers & offsets */ 19 #define V2M_SYSREGS_BASE UL(0x1c010000) 20 #define V2M_SYS_ID UL(0x0) 21 #define V2M_SYS_SWITCH UL(0x4) 22 #define V2M_SYS_LED UL(0x8) 23 #define V2M_SYS_NVFLAGS UL(0x38) 24 #define V2M_SYS_NVFLAGSSET UL(0x38) 25 #define V2M_SYS_NVFLAGSCLR UL(0x3c) 26 #define V2M_SYS_CFGDATA UL(0xa0) 27 #define V2M_SYS_CFGCTRL UL(0xa4) 28 #define V2M_SYS_CFGSTATUS UL(0xa8) 29 30 #define V2M_CFGCTRL_START BIT_32(31) 31 #define V2M_CFGCTRL_RW BIT_32(30) 32 #define V2M_CFGCTRL_FUNC_SHIFT 20 33 #define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) 34 #define V2M_FUNC_CLK_GEN U(0x01) 35 #define V2M_FUNC_TEMP U(0x04) 36 #define V2M_FUNC_DB_RESET U(0x05) 37 #define V2M_FUNC_SCC_CFG U(0x06) 38 #define V2M_FUNC_SHUTDOWN U(0x08) 39 #define V2M_FUNC_REBOOT U(0x09) 40 41 /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ 42 #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) 43 44 /* 45 * V2M sysled bit definitions. The values written to this 46 * register are defined in arch.h & runtime_svc.h. Only 47 * used by the primary cpu to diagnose any cold boot issues. 48 * 49 * SYS_LED[0] - Security state (S=0/NS=1) 50 * SYS_LED[2:1] - Exception Level (EL3-EL0) 51 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 52 * 53 */ 54 #define V2M_SYS_LED_SS_SHIFT 0x0 55 #define V2M_SYS_LED_EL_SHIFT 0x1 56 #define V2M_SYS_LED_EC_SHIFT 0x3 57 58 #define V2M_SYS_LED_SS_MASK U(0x1) 59 #define V2M_SYS_LED_EL_MASK U(0x3) 60 #define V2M_SYS_LED_EC_MASK U(0x1f) 61 62 /* V2M sysid register bits */ 63 #define V2M_SYS_ID_REV_SHIFT 28 64 #define V2M_SYS_ID_HBI_SHIFT 16 65 #define V2M_SYS_ID_BLD_SHIFT 12 66 #define V2M_SYS_ID_ARCH_SHIFT 8 67 #define V2M_SYS_ID_FPGA_SHIFT 0 68 69 #define V2M_SYS_ID_REV_MASK U(0xf) 70 #define V2M_SYS_ID_HBI_MASK U(0xfff) 71 #define V2M_SYS_ID_BLD_MASK U(0xf) 72 #define V2M_SYS_ID_ARCH_MASK U(0xf) 73 #define V2M_SYS_ID_FPGA_MASK U(0xff) 74 75 #define V2M_SYS_ID_BLD_LENGTH 4 76 77 78 /* NOR Flash */ 79 #define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000)) 80 #define V2M_FLASH0_SIZE UL(0x04000000) 81 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 82 83 #define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000)) 84 #define V2M_IOFPGA_SIZE UL(0x03000000) 85 86 /* PL011 UART related constants */ 87 #define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000)) 88 #define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000)) 89 #define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000)) 90 #define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000)) 91 92 #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 93 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 94 #define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 95 #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 96 97 /* SP804 timer related constants */ 98 #define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000)) 99 #define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000)) 100 101 /* SP810 controller */ 102 #define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000)) 103 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) 104 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) 105 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) 106 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21) 107 108 /* 109 * The flash can be mapped either as read-only or read-write. 110 * 111 * If it is read-write then it should also be mapped as device memory because 112 * NOR flash programming involves sending a fixed, ordered sequence of commands. 113 * 114 * If it is read-only then it should also be mapped as: 115 * - Normal memory, because reading from NOR flash is transparent, it is like 116 * reading from RAM. 117 * - Non-executable by default. If some parts of the flash need to be executable 118 * then platform code is responsible for re-mapping the appropriate portion 119 * of it as executable. 120 */ 121 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 122 V2M_FLASH0_SIZE, \ 123 MT_DEVICE | MT_RW | MT_SECURE) 124 125 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 126 V2M_FLASH0_SIZE, \ 127 MT_RO_DATA | MT_SECURE) 128 129 #define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ 130 V2M_IOFPGA_SIZE, \ 131 MT_DEVICE | MT_RW | MT_SECURE) 132 133 /* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */ 134 #define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \ 135 V2M_IOFPGA_BASE, \ 136 V2M_IOFPGA_SIZE, \ 137 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 138 139 140 #endif /* V2M_DEF_H */ 141