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Searched refs:__BL31_END__ (Results 1 – 14 of 14) sorted by relevance

/trusted-firmware-a/bl31/
A Dbl31.ld.S131 __BL31_END__ = .; define
187 __BL31_END__ = .; define
/trusted-firmware-a/plat/renesas/common/include/
A Dplat.ld.S31 ASSERT(__BL31_END__ <= BL31_LIMIT - DEVICE_SRAM_SIZE,
/trusted-firmware-a/plat/mediatek/mt6795/
A Dbl31.ld.S107 __BL31_END__ = .; define
/trusted-firmware-a/include/common/
A Dbl_common.h57 #define __BL31_END__ Load$$LR$$LR_END$$Base macro
126 IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END);
/trusted-firmware-a/plat/nxp/common/setup/include/
A Dplat_common.h20 #define BL31_END (uintptr_t)(&__BL31_END__)
/trusted-firmware-a/build/qemu/release/bl31/
A Dbl31.ld54 __BL31_END__ = .; symbol
A Dbl31.dump433 000000000e05a000 g coherent_ram 0000000000000000 __BL31_END__
790 e0400a4: d00000c1 adrp x1, e05a000 <__BL31_END__>
2316 e04145c: b00000c0 adrp x0, e05a000 <__BL31_END__>
2319 e041468: b00000c7 adrp x7, e05a000 <__BL31_END__>
A Dbl31.map1979 0x000000000e05a000 __BL31_END__ = .
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S88 .quad __BL31_END__ - BL31_BASE
A Dplat_psci_handlers.c270 uint64_t src_len_in_bytes = (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE; in tegra_soc_pwr_domain_power_down_wfi()
/trusted-firmware-a/plat/xilinx/common/
A Dplat_startup.c164 (atf_handoff_addr > (uint64_t)&__BL31_END__)); in fsbl_atf_handover()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c287 uint64_t src_len_in_bytes = (uint64_t)(((uintptr_t)(&__BL31_END__) - in tegra_soc_pwr_domain_power_down_wfi()
/trusted-firmware-a/docs/design/
A Dfirmware-design.rst1659 - ``bl31.map`` link map file provides ``__BL31_END__`` address.
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/
A Dfirmware-design.rst.txt1659 - ``bl31.map`` link map file provides ``__BL31_END__`` address.

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