/trusted-firmware-a/tools/memory/ |
A D | print_memory_map.py | 68 for address in address_list: 69 if "bl1" in address[2]: 70 print(address[0], '+{:-^22}+ |{:^22}| |{:^22}|'.format(address[1], '', '')) 71 elif "bl2" in address[2]: 72 print(address[0], '|{:^22}| +{:-^22}+ |{:^22}|'.format('', address[1], '')) 73 elif "bl31" in address[2]: 74 print(address[0], '|{:^22}| |{:^22}| +{:-^22}+'.format('', '', address[1])) 76 print(address[0], '|{:^22}| |{:^22}| +{:-^22}+'.format('', '', address[1]))
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/trusted-firmware-a/plat/st/common/ |
A D | stm32cubeprogrammer_usb.c | 22 uintptr_t address; member 40 dfu->address = UNDEFINED_DOWN_ADDR; \ 65 dfu->buffer[1] = (uint8_t)(dfu->address); in dfu_callback_upload() 75 dfu->address == UNDEFINED_DOWN_ADDR) { in dfu_callback_upload() 115 *buffer = dfu->address; in dfu_callback_download() 116 dfu->address += *len; in dfu_callback_download() 118 if (dfu->address - dfu->base > dfu->len) { in dfu_callback_download() 131 dfu->phase, alt, dfu->address); in dfu_callback_manifestation() 136 dfu->phase, alt, dfu->address); in dfu_callback_manifestation() 148 dfu->address = UNDEFINED_DOWN_ADDR; in dfu_callback_manifestation() [all …]
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/trusted-firmware-a/plat/arm/board/corstone700/common/drivers/mhu/ |
A D | mhu.c | 30 void mhu_secure_message_start(uintptr_t address, unsigned int slot_id) in mhu_secure_message_start() argument 47 intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_start() 62 void mhu_secure_message_send(uintptr_t address, in mhu_secure_message_send() argument 71 assert((mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_send() 74 MHU_V2_ACCESS_REQUEST(address); in mhu_secure_message_send() 79 access_ready = MHU_V2_IS_ACCESS_READY(address); in mhu_secure_message_send() 91 mmio_write_32(address + CPU_INTR_S_SET, message); in mhu_secure_message_send() 94 void mhu_secure_message_end(uintptr_t address, unsigned int slot_id) in mhu_secure_message_end() argument 101 MHU_V2_CLEAR_REQUEST(address); in mhu_secure_message_end()
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A D | mhu.h | 30 void mhu_secure_message_start(uintptr_t address, unsigned int slot_id); 31 void mhu_secure_message_send(uintptr_t address, 34 void mhu_secure_message_end(uintptr_t address, unsigned int slot_id);
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/trusted-firmware-a/plat/rpi/rpi4/ |
A D | rpi4_pci_svc.c | 46 static uint64_t pci_segment_lib_get_base(uint32_t address, uint32_t offset) in pci_segment_lib_get_base() argument 57 if (address != 0U) { in pci_segment_lib_get_base() 66 bus = PCI_ADDR_BUS(address); in pci_segment_lib_get_base() 67 dev = PCI_ADDR_DEV(address); in pci_segment_lib_get_base() 68 fun = PCI_ADDR_FUN(address); in pci_segment_lib_get_base() 69 address = (bus << PCIE_EXT_BUS_SHIFT) | in pci_segment_lib_get_base() 85 mmio_write_32(PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, address); in pci_segment_lib_get_base()
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/trusted-firmware-a/plat/arm/board/tc/fdts/ |
A D | tc_tb_fw_config.dts | 38 load-address = <0xfee00000>; 42 load-address = <0xfec00000>; 48 load-address = <0xfd280000>; 53 load-address = <0xfe000000>; 59 load-address = <0xfe100000>; 65 load-address = <0xfe200000>; 70 load-address = <0xfe600000>;
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A D | tc_fw_config.dts | 16 load-address = <0x0 0x4001300>; 22 load-address = <0x0 0x04001700>; 28 load-address = <0x0 0x83000000>;
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/trusted-firmware-a/docs/design/ |
A D | reset-design.rst | 30 address" for more information. 32 Programmable CPU reset address 35 By default, TF-A assumes that the CPU reset address is not programmable. 36 Therefore, all CPUs start at the same address (typically address 0) whenever 40 If the reset vector address (reflected in the reset vector base address register 42 at the right address, both on a cold and warm reset. Therefore, the boot type 45 |Reset code flow with programmable reset address| 77 Programmable CPU reset address, Cold boot on a single CPU 81 a programmable CPU reset address and which release a single CPU out of reset. 91 Using BL31 entrypoint as the reset address [all …]
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
A D | reset-design.rst.txt | 30 address" for more information. 32 Programmable CPU reset address 35 By default, TF-A assumes that the CPU reset address is not programmable. 36 Therefore, all CPUs start at the same address (typically address 0) whenever 40 If the reset vector address (reflected in the reset vector base address register 42 at the right address, both on a cold and warm reset. Therefore, the boot type 45 |Reset code flow with programmable reset address| 77 Programmable CPU reset address, Cold boot on a single CPU 81 a programmable CPU reset address and which release a single CPU out of reset. 91 Using BL31 entrypoint as the reset address [all …]
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/trusted-firmware-a/plat/arm/board/fvp/fdts/ |
A D | fvp_fw_config.dts | 16 load-address = <0x0 0x4001300>; 22 load-address = <0x0 0x82000000>; 34 load-address = <0x0 0x04001300>; 42 load-address = <0x0 0x04001500>; 49 load-address = <0x0 0x80000000>;
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A D | optee_sp_manifest.dts | 24 load-address = <0x6280000>; 39 base-address = <0x00000000 0x1c0a0000>; 45 base-address = <0x00000000 0x2f000000>;
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/trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/marvell/armada/misc/ |
A D | mvebu-ccu.rst.txt | 1 Marvell CCU address decoding bindings 4 CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The CCU node includes a description of the address decoding configuration. 22 - Base address of the window
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A D | mvebu-amb.rst.txt | 1 AMB - AXI MBUS address decoding 6 The Runit offers a second level of address windows lookup. It is used to map 10 address space and the properties associated with that address space. 48 - Base address of the window
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A D | mvebu-io-win.rst.txt | 1 Marvell IO WIN address decoding bindings 4 IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The IO WIN includes a description of the address decoding configuration. 9 layer of decoding. This additional address decoding layer defines one of the 33 - Base address of the window
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A D | mvebu-iob.rst.txt | 1 Marvell IOB address decoding bindings 4 IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The IOB includes a description of the address decoding configuration. 9 When a transaction passes through the IOB, its address is compared to each of 26 - Base address of the window
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/trusted-firmware-a/docs/plat/marvell/armada/misc/ |
A D | mvebu-ccu.rst | 1 Marvell CCU address decoding bindings 4 CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The CCU node includes a description of the address decoding configuration. 22 - Base address of the window
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A D | mvebu-amb.rst | 1 AMB - AXI MBUS address decoding 6 The Runit offers a second level of address windows lookup. It is used to map 10 address space and the properties associated with that address space. 48 - Base address of the window
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A D | mvebu-io-win.rst | 1 Marvell IO WIN address decoding bindings 4 IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The IO WIN includes a description of the address decoding configuration. 9 layer of decoding. This additional address decoding layer defines one of the 33 - Base address of the window
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A D | mvebu-iob.rst | 1 Marvell IOB address decoding bindings 4 IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs. 6 The IOB includes a description of the address decoding configuration. 9 When a transaction passes through the IOB, its address is compared to each of 26 - Base address of the window
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/trusted-firmware-a/fdts/ |
A D | stm32mp15-fw-config.dtsi | 35 load-address = <0x0 STM32MP_HW_CONFIG_BASE>; 41 load-address = <0x0 STM32MP_BL33_BASE>; 48 load-address = <0x0 STM32MP_OPTEE_BASE>; 54 load-address = <0x0 STM32MP_BL32_BASE>; 60 load-address = <0x0 STM32MP_BL32_DTB_BASE>;
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A D | fvp-ve-Cortex-A7x1.dts | 13 #address-cells = <2>; 17 #address-cells = <2>; 35 #address-cells = <0>; 55 #address-cells = <2>;
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A D | fvp-foundation-gicv2-psci.dts | 26 #address-cells = <2>; 50 #address-cells = <2>; 93 #address-cells = <0>; 119 #address-cells = <2>; 140 #address-cells = <2>;
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A D | fvp-foundation-gicv3-psci.dts | 26 #address-cells = <2>; 50 #address-cells = <2>; 93 #address-cells = <2>; 128 #address-cells = <2>; 149 #address-cells = <2>;
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A D | stm32mp157c-ev1.dts | 34 #address-cells = <1>; 44 #address-cells = <1>; 53 #address-cells = <1>;
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/trusted-firmware-a/plat/marvell/armada/common/ |
A D | marvell_pm.c | 24 void marvell_program_mailbox(uintptr_t address) in marvell_program_mailbox() argument 37 mailbox[MBOX_IDX_SEC_ADDR] = address; in marvell_program_mailbox()
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