| /trusted-firmware-a/common/ |
| A D | fdt_fixup.c | 200 uint32_t addresses[4]; in fdt_add_reserved_memory() local
217 addresses[idx] = cpu_to_fdt32(HIGH_BITS(base)); in fdt_add_reserved_memory()
220 addresses[idx] = cpu_to_fdt32(base & 0xffffffff); in fdt_add_reserved_memory()
223 addresses[idx] = cpu_to_fdt32(HIGH_BITS(size)); in fdt_add_reserved_memory()
226 addresses[idx] = cpu_to_fdt32(size & 0xffffffff); in fdt_add_reserved_memory()
230 fdt_setprop(dtb, offs, "reg", addresses, idx * sizeof(uint32_t)); in fdt_add_reserved_memory()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/arm_fpga/ |
| A D | index.rst.txt | 13 configuration: the UART and GIC base addresses are read from there.
70 This will use the default load addresses as described above. When those
71 addresses need to differ for a certain setup, they can be passed on the
87 components at their respective load addresses. In addition to this file
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| /trusted-firmware-a/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 13 configuration: the UART and GIC base addresses are read from there.
70 This will use the default load addresses as described above. When those
71 addresses need to differ for a certain setup, they can be passed on the
87 components at their respective load addresses. In addition to this file
|
| /trusted-firmware-a/tools/marvell/doimage/secure/ |
| A D | sec_img_7K.cfg | 27 # Two register addresses for each connected CP
|
| A D | sec_img_8K.cfg | 27 # Two register addresses for each connected CP
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | allwinner.rst.txt | 89 address space. So the virtual addresses used in BL31 match the physical
90 addresses as presented above.
|
| A D | rpi4.rst.txt | 73 memory. The load addresses have a default, but can also be changed by
75 armstub image file, it will put those two load addresses in memory locations
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| A D | intel-agilex.rst.txt | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
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| A D | intel-stratix10.rst.txt | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
|
| A D | rpi3.rst.txt | 62 between them so that the addresses they are loaded to match the ones specified
89 All addresses are Physical Addresses from the point of view of the Arm cores.
139 different mappings than the Arm cores in which the I/O addresses don't overlap
197 The build system concatenates BL1 and the FIP so that the addresses match the
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| /trusted-firmware-a/docs/plat/ |
| A D | allwinner.rst | 89 address space. So the virtual addresses used in BL31 match the physical
90 addresses as presented above.
|
| A D | rpi4.rst | 73 memory. The load addresses have a default, but can also be changed by
75 armstub image file, it will put those two load addresses in memory locations
|
| A D | intel-agilex.rst | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
|
| A D | intel-stratix10.rst | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
|
| A D | rpi3.rst | 62 between them so that the addresses they are loaded to match the ones specified
89 All addresses are Physical Addresses from the point of view of the Arm cores.
139 different mappings than the Arm cores in which the I/O addresses don't overlap
197 The build system concatenates BL1 and the FIP so that the addresses match the
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| /trusted-firmware-a/plat/allwinner/common/ |
| A D | arisc_off.S | 81 # same as above, but with the MMIO addresses matching the H6 SoC
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| /trusted-firmware-a/plat/nvidia/tegra/scat/ |
| A D | bl31.scat | 74 * security. GOT is a table of addresses so ensure 8-byte alignment.
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| /trusted-firmware-a/docs/components/ |
| A D | xlat-tables-lib-v2-design.rst | 39 removing all mentions of virtual addresses). Although potential bug fixes will
112 the MPU's translations are limited to specification of valid addresses and
113 access permissions. If the requested virtual and physical addresses mismatch
395 directly maps regions by "base" and "limit" (bottom and top) addresses.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | xlat-tables-lib-v2-design.rst.txt | 39 removing all mentions of virtual addresses). Although potential bug fixes will
112 the MPU's translations are limited to specification of valid addresses and
113 access permissions. If the requested virtual and physical addresses mismatch
395 directly maps regions by "base" and "limit" (bottom and top) addresses.
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| /trusted-firmware-a/docs/getting_started/ |
| A D | build-options.rst | 458 - ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
459 bottom, higher addresses at the top. This build flag can be set to '1' to
460 invert this behavior. Lower addresses will be printed at the top and higher
461 addresses at the bottom.
886 Using ``-O0`` could cause output images to be larger and base addresses
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/getting_started/ |
| A D | build-options.rst.txt | 458 - ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
459 bottom, higher addresses at the top. This build flag can be set to '1' to
460 invert this behavior. Lower addresses will be printed at the top and higher
461 addresses at the bottom.
886 Using ``-O0`` could cause output images to be larger and base addresses
|
| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | change-log.md.txt | 1757 - NV-counter base addresses are now loaded from the device tree when
1765 - DTB and BL33 load addresses have been given sensible default values
1766 - Now reads generic timer counter frequency, GICD and GICR base addresses,
2233 controller, and eMMC controller base addresses configurable
2296 - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC code
3406 attempt to access addresses in the higher VA range.
3766 - Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
4300 - It is now possible to map higher physical addresses using non-flat virtual to
4535 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to
4663 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to
[all …]
|
| /trusted-firmware-a/docs/ |
| A D | change-log.md | 1757 - NV-counter base addresses are now loaded from the device tree when
1765 - DTB and BL33 load addresses have been given sensible default values
1766 - Now reads generic timer counter frequency, GICD and GICR base addresses,
2233 controller, and eMMC controller base addresses configurable
2296 - allwinner: Fix H6 GPIO and CCU memory map addresses and incorrect ARISC code
3406 attempt to access addresses in the higher VA range.
3766 - Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
4300 - It is now possible to map higher physical addresses using non-flat virtual to
4535 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to
4663 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to
[all …]
|
| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 1549 correspond to particular addresses. TF-A code can refer to these symbols to
1640 How to choose the right base addresses for each bootloader stage image
1645 locations and the base addresses of each image must be chosen carefully such
1647 the base addresses might need adjustments to cope with the new memory layout.
1650 general recipe for choosing the right base addresses for each bootloader image.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 1549 correspond to particular addresses. TF-A code can refer to these symbols to
1640 How to choose the right base addresses for each bootloader stage image
1645 locations and the base addresses of each image must be chosen carefully such
1647 the base addresses might need adjustments to cope with the new memory layout.
1650 general recipe for choosing the right base addresses for each bootloader image.
|