| /trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | mce.c | 177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
206 ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); in mce_command_handler()
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
237 ret = ops->online_core(cpu_ari_base, arg0); in mce_command_handler()
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
248 arg0); in mce_command_handler()
251 write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ? in mce_command_handler()
260 arg0); in mce_command_handler()
273 TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); in mce_command_handler()
[all …]
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| /trusted-firmware-a/bl2/ |
| A D | bl2_main.c | 33 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_el3_setup() argument
37 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_el3_setup()
54 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_setup() argument
58 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_setup()
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| /trusted-firmware-a/plat/rockchip/rk3399/ |
| A D | plat_sip_calls.c | 30 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, in ddr_smc_handler() argument
35 return ddr_set_rate((uint32_t)arg0); in ddr_smc_handler()
37 return ddr_round_rate((uint32_t)arg0); in ddr_smc_handler()
41 dram_set_odt_pd(arg0, arg1, arg2); in ddr_smc_handler()
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| /trusted-firmware-a/plat/arm/common/sp_min/ |
| A D | arm_sp_min_setup.c | 96 bl33_image_ep_info.args.arg0 = 0U; in arm_sp_min_early_platform_setup()
136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
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| /trusted-firmware-a/plat/arm/css/sgm/ |
| A D | sgm_bl31_setup.c | 28 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
34 bl_params = ((bl_params_t *)arg0)->head; in bl31_early_platform_setup2()
49 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| /trusted-firmware-a/plat/rpi/rpi3/ |
| A D | rpi3_bl31_setup.c | 70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
84 bl_params_t *params_from_bl2 = (bl_params_t *) arg0; in bl31_early_platform_setup2()
122 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
133 bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
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| /trusted-firmware-a/plat/arm/board/corstone700/sp_min/ |
| A D | corstone700_sp_min_setup.c | 9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /trusted-firmware-a/plat/arm/board/fvp_ve/sp_min/ |
| A D | fvp_ve_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /trusted-firmware-a/plat/brcm/common/ |
| A D | brcm_bl31_setup.c | 133 bl33_image_ep_info.args.arg0 = (u_register_t)PRELOADED_DTB_BASE; in brcm_bl31_early_platform_setup()
181 bl33_image_ep_info.args.arg0 = (u_register_t)BL33_SHARED_DDR_BASE; in brcm_bl31_early_platform_setup()
188 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
195 brcm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
197 plat_bcm_bl31_early_platform_setup((void *)arg0, (void *)arg3); in bl31_early_platform_setup2()
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| A D | brcm_bl2_setup.c | 64 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
158 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in bcm_bl2_handle_post_image_load()
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| /trusted-firmware-a/plat/arm/board/a5ds/ |
| A D | a5ds_bl2_setup.c | 9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a/plat/arm/board/a5ds/sp_min/ |
| A D | a5ds_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /trusted-firmware-a/include/bl2/ |
| A D | bl2.h | 12 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
14 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
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| /trusted-firmware-a/plat/arm/board/fvp_ve/ |
| A D | fvp_ve_bl2_setup.c | 16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a/bl32/tsp/ |
| A D | tsp_private.h | 74 tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
83 tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
132 tsp_args_t *tsp_system_reset_main(uint64_t arg0,
141 tsp_args_t *tsp_system_off_main(uint64_t arg0,
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| /trusted-firmware-a/plat/arm/board/fvp/sp_min/ |
| A D | fvp_sp_min_setup.c | 18 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
21 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /trusted-firmware-a/plat/layerscape/board/ls1043/ |
| A D | ls1043_bl31_setup.c | 18 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
38 ls_bl31_early_platform_setup((void *)arg0, (void *)arg3); in bl31_early_platform_setup2()
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| /trusted-firmware-a/lib/optee/ |
| A D | optee_utils.c | 180 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
182 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
223 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
226 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
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| /trusted-firmware-a/plat/qemu/common/ |
| A D | qemu_bl2_setup.c | 29 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
177 bl_mem_params->ep_info.args.arg0 = in qemu_bl2_handle_post_image_load()
202 bl_mem_params->ep_info.args.arg0 = in qemu_bl2_handle_post_image_load()
209 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in qemu_bl2_handle_post_image_load()
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| /trusted-firmware-a/plat/arm/common/ |
| A D | arm_bl31_setup.c | 147 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in arm_bl31_early_platform_setup()
227 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in arm_bl31_early_platform_setup()
229 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; in arm_bl31_early_platform_setup()
237 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
240 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| /trusted-firmware-a/plat/arm/css/common/ |
| A D | css_bl2_setup.c | 56 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a/plat/arm/board/juno/ |
| A D | juno_bl31_setup.c | 15 void __init bl31_early_platform_setup2(u_register_t arg0, in bl31_early_platform_setup2() argument
30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| /trusted-firmware-a/plat/mediatek/mt6795/ |
| A D | bl31_plat_setup.c | 177 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
180 struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0; in bl31_early_platform_setup2()
357 next_image_info->args.arg0 = get_kernel_info_r0(); in bl31_plat_get_next_kernel64_ep_info()
362 next_image_info->args.arg0, in bl31_plat_get_next_kernel64_ep_info()
401 next_image_info->args.arg0 = get_kernel_info_r0(); in bl31_plat_get_next_kernel32_ep_info()
407 next_image_info->args.arg0, in bl31_plat_get_next_kernel32_ep_info()
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| A D | mce.c | 43 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler() argument
50 ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); in mce_command_handler()
66 ret = nvg_online_core((uint32_t)arg0); in mce_command_handler()
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| /trusted-firmware-a/plat/arm/board/tc/ |
| A D | tc_bl31_setup.c | 43 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
46 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
|