/trusted-firmware-a/plat/xilinx/zynqmp/pm_service/ |
A D | pm_api_ioctl.c | 616 unsigned int arg1, in pm_api_ioctl() argument 627 ret = pm_ioctl_set_rpu_oper_mode(arg1); in pm_api_ioctl() 630 ret = pm_ioctl_config_boot_addr(nid, arg1); in pm_api_ioctl() 633 ret = pm_ioctl_config_tcm_comb(arg1); in pm_api_ioctl() 639 ret = pm_ioctl_set_sgmii_mode(nid, arg1); in pm_api_ioctl() 642 ret = pm_ioctl_sd_dll_reset(nid, arg1); in pm_api_ioctl() 660 ret = pm_ioctl_write_ggs(arg1, arg2); in pm_api_ioctl() 663 ret = pm_ioctl_read_ggs(arg1, value); in pm_api_ioctl() 666 ret = pm_ioctl_write_pggs(arg1, arg2); in pm_api_ioctl() 669 ret = pm_ioctl_read_pggs(arg1, value); in pm_api_ioctl() [all …]
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A D | pm_api_sys.c | 43 #define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \ argument 44 pl[1] = (uint32_t)(arg1); \ 48 #define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \ argument 50 PM_PACK_PAYLOAD2(pl, arg0, arg1); \ 53 #define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \ argument 55 PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \ 60 PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \ 65 PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \ 773 unsigned int arg1, in pm_ioctl() argument 1326 pm_clock_get_name(arg1, (char *)data); in pm_query_data() [all …]
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/trusted-firmware-a/plat/arm/board/juno/ |
A D | juno_bl31_setup.c | 16 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument 20 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2() 23 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2() 27 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2() 30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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/trusted-firmware-a/services/arm_arch_svc/ |
A D | arm_arch_svc_setup.c | 32 static int32_t smccc_arch_features(u_register_t arg1) in smccc_arch_features() argument 34 switch (arg1) { in smccc_arch_features() 39 return plat_is_smccc_feature_available(arg1); in smccc_arch_features() 96 static int32_t smccc_arch_id(u_register_t arg1) in smccc_arch_id() argument 98 if (arg1 == SMCCC_GET_SOC_REVISION) { in smccc_arch_id() 101 if (arg1 == SMCCC_GET_SOC_VERSION) { in smccc_arch_id()
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/trusted-firmware-a/plat/arm/board/fvp/ |
A D | fvp_bl31_setup.c | 21 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument 26 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2() 28 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2() 32 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2() 36 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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A D | fvp_bl2_setup.c | 21 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument 23 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2() 68 ep_info->args.arg1 = (uint32_t)fw_config_base; in plat_get_next_bl_params()
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/trusted-firmware-a/plat/mediatek/mt8192/drivers/dfd/ |
A D | plat_dfd.c | 112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument 119 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher() 123 if (arg1 <= 0x200) { in dfd_smc_dispatcher() 124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher() 129 if (arg1 <= 0x200) { in dfd_smc_dispatcher() 130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/ |
A D | mce.c | 177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler() 191 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, in mce_command_handler() 215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler() 220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler() 228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler() 242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler() 296 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler() 300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler() 306 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler() 337 write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1)); in mce_command_handler() [all …]
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/trusted-firmware-a/bl32/tsp/ |
A D | tsp_private.h | 67 uint64_t arg1, 75 uint64_t arg1, 84 uint64_t arg1, 115 uint64_t arg1, 124 uint64_t arg1, 133 uint64_t arg1, 142 uint64_t arg1,
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A D | tsp_main.c | 49 uint64_t arg1, in set_smc_args() argument 67 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); in set_smc_args() 171 uint64_t arg1, in tsp_cpu_off_main() argument 214 uint64_t arg1, in tsp_cpu_suspend_main() argument 256 uint64_t arg1, in tsp_cpu_resume_main() argument 294 uint64_t arg1, in tsp_system_off_main() argument 326 uint64_t arg1, in tsp_system_reset_main() argument 360 uint64_t arg1, in tsp_smc_handler() argument 390 results[0] = arg1; in tsp_smc_handler() 444 uint64_t arg1, in tsp_abort_smc_handler() argument
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/trusted-firmware-a/plat/mediatek/mt8195/drivers/dfd/ |
A D | plat_dfd.c | 128 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument 136 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher() 140 if (arg1 <= 0x200) { in dfd_smc_dispatcher() 141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher() 146 if (arg1 <= 0x200) { in dfd_smc_dispatcher() 147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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/trusted-firmware-a/drivers/arm/css/scmi/ |
A D | scmi_private.h | 97 #define SCMI_PAYLOAD_ARG1(payld_arr, arg1) \ argument 98 mmio_write_32((uintptr_t)&payld_arr[0], arg1) 100 #define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ argument 101 SCMI_PAYLOAD_ARG1(payld_arr, arg1); \ 105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument 106 SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \
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/trusted-firmware-a/bl2/ |
A D | bl2_main.c | 33 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_el3_setup() argument 37 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_el3_setup() 54 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_setup() argument 58 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_setup()
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/trusted-firmware-a/plat/arm/common/sp_min/ |
A D | arm_sp_min_setup.c | 97 bl33_image_ep_info.args.arg1 = ~0U; in arm_sp_min_early_platform_setup() 136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument 139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup() 158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument 161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
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/trusted-firmware-a/plat/arm/board/tc/ |
A D | tc_bl31_setup.c | 43 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument 46 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2() 49 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
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/trusted-firmware-a/plat/xilinx/versal/pm_service/ |
A D | pm_api_sys.c | 48 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ argument 49 pl[1] = (uint32_t)(arg1); \ 55 PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1); \ 60 PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2); \ 65 PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3); \ 829 arg1, arg2, arg3); in pm_query_data() 863 uint32_t arg1, uint32_t arg2, uint32_t *value, in pm_api_ioctl() argument 871 return pm_pll_set_mode(arg1, arg2, flag); in pm_api_ioctl() 873 return pm_pll_get_mode(arg1, value, flag); in pm_api_ioctl() 880 ret = pm_register_sgi(arg1); in pm_api_ioctl() [all …]
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/trusted-firmware-a/plat/qemu/common/ |
A D | qemu_bl2_setup.c | 29 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument 32 meminfo_t *mem_layout = (void *)arg1; in bl2_early_platform_setup2() 178 bl_mem_params->ep_info.args.arg1; in qemu_bl2_handle_post_image_load() 179 bl_mem_params->ep_info.args.arg1 = 0; in qemu_bl2_handle_post_image_load() 204 bl_mem_params->ep_info.args.arg1 = 0U; in qemu_bl2_handle_post_image_load()
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/trusted-firmware-a/plat/rpi/rpi3/ |
A D | rpi3_bl31_setup.c | 70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument 81 assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL); in bl31_early_platform_setup2() 123 bl33_image_ep_info.args.arg1 = ~0U; in bl31_early_platform_setup2() 134 bl33_image_ep_info.args.arg1 = 0ULL; in bl31_early_platform_setup2()
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/trusted-firmware-a/plat/arm/board/corstone700/sp_min/ |
A D | corstone700_sp_min_setup.c | 9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument 12 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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/trusted-firmware-a/plat/arm/board/fvp_ve/sp_min/ |
A D | fvp_ve_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument 14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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/trusted-firmware-a/plat/layerscape/board/ls1043/ |
A D | ls1043_bl2_setup.c | 12 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument 15 ls_bl2_early_platform_setup((meminfo_t *)arg1); in bl2_early_platform_setup2()
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/trusted-firmware-a/plat/arm/board/a5ds/ |
A D | a5ds_bl2_setup.c | 9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument 12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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/trusted-firmware-a/plat/arm/board/a5ds/sp_min/ |
A D | a5ds_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument 14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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/trusted-firmware-a/include/bl2/ |
A D | bl2.h | 12 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, 14 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
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/trusted-firmware-a/plat/imx/imx7/common/ |
A D | imx7_bl2_el3_common.c | 87 bl_mem_params->ep_info.args.arg1; in bl2_plat_handle_post_image_load() 88 bl_mem_params->ep_info.args.arg1 = 0; in bl2_plat_handle_post_image_load() 150 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, in bl2_el3_early_platform_setup() argument 166 imx7_platform_setup(arg1, arg2, arg3, arg4); in bl2_el3_early_platform_setup()
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