| /trusted-firmware-a/drivers/st/gpio/ |
| A D | stm32_gpio.c | 35 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); in ckeck_gpio_bank()
98 uint32_t bank; in dt_set_gpio_config() local
206 uintptr_t base = stm32_get_gpio_bank_base(bank); in set_gpio()
246 VERBOSE("GPIO %u mode set to 0x%x\n", bank, in set_gpio()
248 VERBOSE("GPIO %u speed set to 0x%x\n", bank, in set_gpio()
250 VERBOSE("GPIO %u mode pull to 0x%x\n", bank, in set_gpio()
260 stm32mp_register_secure_gpio(bank, pin); in set_gpio()
261 set_gpio_secure_cfg(bank, pin, true); in set_gpio()
264 stm32mp_register_non_secure_gpio(bank, pin); in set_gpio()
265 set_gpio_secure_cfg(bank, pin, false); in set_gpio()
[all …]
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| /trusted-firmware-a/plat/st/stm32mp1/ |
| A D | stm32mp1_private.c | 101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) in stm32_get_gpio_bank_base() argument
103 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_base()
107 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); in stm32_get_gpio_bank_base()
109 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); in stm32_get_gpio_bank_base()
114 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_offset()
118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); in stm32_get_gpio_bank_offset()
120 return bank * GPIO_BANK_OFFSET; in stm32_get_gpio_bank_offset()
125 if (bank == GPIO_BANK_Z) { in stm32_get_gpio_bank_clock()
129 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); in stm32_get_gpio_bank_clock()
131 return GPIOA + (bank - GPIO_BANK_A); in stm32_get_gpio_bank_clock()
[all …]
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| A D | stm32mp1_shared_resources.c | 112 static unsigned int get_gpio_nbpin(unsigned int bank) in get_gpio_nbpin() argument
114 if (bank != GPIO_BANK_Z) { in get_gpio_nbpin()
115 int count = fdt_get_gpio_bank_pin_count(bank); in get_gpio_nbpin()
314 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin) in stm32mp_register_secure_gpio() argument
316 switch (bank) { in stm32mp_register_secure_gpio()
321 ERROR("GPIO bank %u cannot be secured\n", bank); in stm32mp_register_secure_gpio()
328 switch (bank) { in stm32mp_register_non_secure_gpio()
337 static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank) in stm32mp_gpio_bank_is_non_secure() argument
344 if (bank != GPIO_BANK_Z) { in stm32mp_gpio_bank_is_non_secure()
357 static bool stm32mp_gpio_bank_is_secure(unsigned int bank) in stm32mp_gpio_bank_is_secure() argument
[all …]
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| /trusted-firmware-a/plat/st/common/include/ |
| A D | stm32mp_shared_resources.h | 33 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
34 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
48 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, in stm32mp_register_secure_gpio()
53 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, in stm32mp_register_non_secure_gpio()
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| A D | stm32mp_common.h | 64 uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
65 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
66 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
69 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
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| A D | stm32mp_dt.h | 41 int fdt_get_gpio_bank_pin_count(unsigned int bank);
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| /trusted-firmware-a/drivers/st/bsec/ |
| A D | bsec.c | 127 uint32_t bank = otp_bank_offset(otp); in bsec_check_error() local
577 uint32_t bank = otp_bank_offset(otp); in bsec_write_sr_lock() local
583 bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); in bsec_write_sr_lock()
621 uint32_t bank = otp_bank_offset(otp); in bsec_read_sr_lock() local
638 uint32_t bank = otp_bank_offset(otp); in bsec_write_sw_lock() local
644 bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank); in bsec_write_sw_lock()
682 uint32_t bank = otp_bank_offset(otp); in bsec_read_sw_lock() local
699 uint32_t bank = otp_bank_offset(otp); in bsec_write_sp_lock() local
743 uint32_t bank = otp_bank_offset(otp); in bsec_read_sp_lock() local
757 uint32_t bank = otp_bank_offset(otp); in bsec_wr_lock() local
[all …]
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| /trusted-firmware-a/plat/rockchip/rk3399/drivers/gpio/ |
| A D | rk3399_gpio.c | 163 uint32_t bank = GET_GPIO_BANK(gpio); in get_pull() local
167 assert((port < 5) && (bank < 4)); in get_pull()
173 port * 16 + bank * 4); in get_pull()
177 (port - 2) * 16 + bank * 4); in get_pull()
190 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in get_pull()
205 uint32_t bank = GET_GPIO_BANK(gpio); in set_pull() local
209 assert((port < 5) && (bank < 4)); in set_pull()
221 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in set_pull()
232 port * 16 + bank * 4, in set_pull()
236 (port - 2) * 16 + bank * 4, in set_pull()
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| /trusted-firmware-a/drivers/st/fmc/ |
| A D | stm32_fmc2_nand.c | 799 uint8_t bank; in stm32_fmc2_init() local
830 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
831 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { in stm32_fmc2_init()
834 bank_assigned |= BIT(bank); in stm32_fmc2_init()
861 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
862 if (bank >= MAX_BANK) { in stm32_fmc2_init()
866 bank_address[bank]; in stm32_fmc2_init()
869 if (bank >= MAX_BANK) { in stm32_fmc2_init()
873 bank_address[bank]; in stm32_fmc2_init()
876 if (bank >= MAX_BANK) { in stm32_fmc2_init()
[all …]
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| /trusted-firmware-a/include/drivers/st/ |
| A D | stm32_gpio.h | 52 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
54 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
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| /trusted-firmware-a/fdts/ |
| A D | stm32mp151.dtsi | 523 st,bank-name = "GPIOA";
534 st,bank-name = "GPIOB";
545 st,bank-name = "GPIOC";
556 st,bank-name = "GPIOD";
567 st,bank-name = "GPIOE";
578 st,bank-name = "GPIOF";
589 st,bank-name = "GPIOG";
600 st,bank-name = "GPIOH";
611 st,bank-name = "GPIOI";
622 st,bank-name = "GPIOJ";
[all …]
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| A D | corstone700_fvp.dts | 23 bank-width = <4>;
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| A D | n1sdp-single-chip.dts | 23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
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| A D | morello-fvp.dts | 79 /* The first bank of memory, memory map is actually provided by UEFI. */
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| A D | rtsm_ve-motherboard.dtsi | 18 bank-width = <4>;
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| A D | rtsm_ve-motherboard-aarch32.dtsi | 19 bank-width = <4>;
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| /trusted-firmware-a/drivers/renesas/common/ddr/ddr_b/ |
| A D | boot_init_dram_regdef.h | 24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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| /trusted-firmware-a/plat/st/common/ |
| A D | stm32mp_dt.c | 317 int fdt_get_gpio_bank_pin_count(unsigned int bank) in fdt_get_gpio_bank_pin_count() argument
323 pinctrl_node = stm32_get_gpio_bank_pinctrl_node(fdt, bank); in fdt_get_gpio_bank_pin_count()
328 bank_offset = stm32_get_gpio_bank_offset(bank); in fdt_get_gpio_bank_pin_count()
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| /trusted-firmware-a/plat/intel/soc/agilex/soc/ |
| A D | agilex_memory_controller.c | 175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
191 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a/plat/intel/soc/stratix10/soc/ |
| A D | s10_memory_controller.c | 204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
220 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | ls1043a.rst.txt | 84 Then change to Alt bank and boot up TF-A:
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| /trusted-firmware-a/docs/plat/ |
| A D | ls1043a.rst | 84 Then change to Alt bank and boot up TF-A:
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| /trusted-firmware-a/plat/intel/soc/common/drivers/qspi/ |
| A D | cadence_qspi.c | 225 int cad_qspi_device_bank_select(uint32_t bank) in cad_qspi_device_bank_select() argument
234 0, 1, &bank); in cad_qspi_device_bank_select()
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| /trusted-firmware-a/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 102 - DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h i…
249 -- Then reset to alternate bank to boot up ATF.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/nxp/ |
| A D | nxp-layerscape.rst.txt | 102 - DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h i…
249 -- Then reset to alternate bank to boot up ATF.
|