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Searched refs:base_addr (Results 1 – 25 of 43) sorted by relevance

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/trusted-firmware-a/drivers/cfi/v2m/
A Dv2m_flash.c40 status = mmio_read_32(base_addr); in nor_status()
58 status = mmio_read_32(base_addr); in nor_poll_dws()
77 status = nor_status(base_addr); in nor_full_status_check()
88 mmio_write_32(base_addr, NOR_2X16(cmd)); in nor_send_cmd()
108 mmio_write_32(base_addr, data); in nor_word_program()
114 status = mmio_read_32(base_addr); in nor_word_program()
123 ret = nor_full_status_check(base_addr); in nor_word_program()
135 int nor_erase(uintptr_t base_addr) in nor_erase() argument
146 ret = nor_full_status_check(base_addr); in nor_erase()
158 int nor_lock(uintptr_t base_addr) in nor_lock() argument
[all …]
/trusted-firmware-a/drivers/imx/uart/
A Dimx_uart.c72 write_reg(base_addr, IMX_UART_CR2_OFFSET, 0); in console_imx_uart_core_init()
74 val = read_reg(base_addr, IMX_UART_CR2_OFFSET); in console_imx_uart_core_init()
83 write_reg(base_addr, IMX_UART_CR2_OFFSET, val); in console_imx_uart_core_init()
87 write_reg(base_addr, IMX_UART_CR3_OFFSET, val); in console_imx_uart_core_init()
99 write_reg(base_addr, IMX_UART_FCR_OFFSET, val); in console_imx_uart_core_init()
115 write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f); in console_imx_uart_core_init()
117 write_reg(base_addr, IMX_UART_BMR_OFFSET, val); in console_imx_uart_core_init()
137 console_imx_uart_core_putc('\r', base_addr); in console_imx_uart_core_putc()
140 write_reg(base_addr, IMX_UART_TXD_OFFSET, c); in console_imx_uart_core_putc()
162 val = read_reg(base_addr, IMX_UART_TS_OFFSET); in console_imx_uart_core_getc()
[all …]
/trusted-firmware-a/drivers/arm/pl061/
A Dpl061_gpio.c50 uintptr_t base_addr; in pl061_get_direction() local
55 base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061]; in pl061_get_direction()
57 data = mmio_read_8(base_addr + PL061_GPIO_DIR); in pl061_get_direction()
65 uintptr_t base_addr; in pl061_set_direction() local
74 mmio_write_8(base_addr + PL061_GPIO_DIR, data); in pl061_set_direction()
77 mmio_write_8(base_addr + PL061_GPIO_DIR, data); in pl061_set_direction()
91 uintptr_t base_addr; in pl061_get_value() local
98 if (mmio_read_8(base_addr + BIT(offset + 2))) in pl061_get_value()
110 uintptr_t base_addr; in pl061_set_value() local
120 mmio_write_8(base_addr + BIT(offset + 2), 0); in pl061_set_value()
[all …]
/trusted-firmware-a/drivers/marvell/
A Damb_adec.c46 uint32_t base_addr; in amb_check_win() local
49 if (win->base_addr > AMB_BASE_ADDR_MASK) { in amb_check_win()
51 win_num, win->base_addr); in amb_check_win()
52 win->base_addr = AMB_BASE_ADDR_MASK; in amb_check_win()
53 WARN("Set the base address to 0x%" PRIx64 "\n", win->base_addr); in amb_check_win()
56 base_addr = win->base_addr << AMB_BASE_OFFSET; in amb_check_win()
59 if (IS_NOT_ALIGN(base_addr, AMB_WIN_ALIGNMENT_1M)) { in amb_check_win()
60 win->base_addr = ALIGN_UP(base_addr, AMB_WIN_ALIGNMENT_1M); in amb_check_win()
63 WARN("Align up the base address to 0x%" PRIx64 "\n", win->base_addr); in amb_check_win()
86 base = win->base_addr << AMB_BASE_OFFSET; in amb_enable_win()
A Diob.c59 if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) { in iob_win_check()
60 win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT); in iob_win_check()
64 win->base_addr); in iob_win_check()
93 end_addr = (win->base_addr + win->win_size - 1); in iob_enable_win()
94 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); in iob_enable_win()
A Dio_win.c48 if (IS_NOT_ALIGN(win->base_addr, IO_WIN_ALIGNMENT_1M)) { in io_win_check()
49 win->base_addr = ALIGN_UP(win->base_addr, IO_WIN_ALIGNMENT_1M); in io_win_check()
51 __func__, win->base_addr); in io_win_check()
79 end_addr = (win->base_addr + win->win_size - 1); in io_win_enable_window()
81 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); in io_win_enable_window()
147 if ((win->target_id != target) || (win->base_addr != base)) { in iow_temp_win_remove()
A Dgwin.c53 if (IS_NOT_ALIGN(win->base_addr, GWIN_ALIGNMENT_64M)) { in gwin_check()
54 win->base_addr &= ~(GWIN_ALIGNMENT_64M - 1); in gwin_check()
56 __func__, win->base_addr); in gwin_check()
79 end_addr = (win->base_addr + win->win_size - 1); in gwin_enable_window()
81 alr = (uint32_t)((win->base_addr >> ADDRESS_RSHIFT) << ADDRESS_LSHIFT); in gwin_enable_window()
A Dccu.c103 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { in ccu_win_check()
104 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); in ccu_win_check()
106 __func__, win->base_addr); in ccu_win_check()
134 end_addr = (win->base_addr + win->win_size - 1); in ccu_enable_win()
135 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); in ccu_enable_win()
202 if ((win->target_id != target) || (win->base_addr != base)) { in ccu_temp_win_remove()
/trusted-firmware-a/lib/pmf/
A Dpmf_main.c192 static inline uintptr_t calc_ts_addr(uintptr_t base_addr, in calc_ts_addr() argument
197 assert(base_addr >= PMF_TIMESTAMP_ARRAY_START); in calc_ts_addr()
198 assert(base_addr < ((PMF_TIMESTAMP_ARRAY_START + in calc_ts_addr()
202 base_addr += ((cpuid * PMF_PERCPU_TIMESTAMP_SIZE) + in calc_ts_addr()
205 return base_addr; in calc_ts_addr()
214 void __pmf_store_timestamp(uintptr_t base_addr, in __pmf_store_timestamp() argument
218 unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr, in __pmf_store_timestamp()
228 void __pmf_store_timestamp_with_cache_maint(uintptr_t base_addr, in __pmf_store_timestamp_with_cache_maint() argument
232 unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr, in __pmf_store_timestamp_with_cache_maint()
243 unsigned long long __pmf_get_timestamp(uintptr_t base_addr, in __pmf_get_timestamp() argument
[all …]
/trusted-firmware-a/include/drivers/cfi/
A Dv2m_flash.h39 void nor_send_cmd(uintptr_t base_addr, unsigned long cmd);
40 int nor_word_program(uintptr_t base_addr, unsigned long data);
41 int nor_lock(uintptr_t base_addr);
42 int nor_unlock(uintptr_t base_addr);
43 int nor_erase(uintptr_t base_addr);
/trusted-firmware-a/include/lib/pmf/
A Dpmf_helpers.h178 uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
180 __pmf_store_timestamp(base_addr, \
191 uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
194 base_addr, (uint64_t)tid, ts); \
209 uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
210 return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\
216 uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
217 return __pmf_get_timestamp(base_addr, tid, \
246 void __pmf_store_timestamp(uintptr_t base_addr,
249 void __pmf_store_timestamp_with_cache_maint(uintptr_t base_addr,
[all …]
/trusted-firmware-a/include/drivers/arm/
A Dsp804_delay_timer.h16 void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops);
18 #define sp804_timer_init(base_addr, clk_mult, clk_div) \ argument
25 sp804_timer_ops_init((base_addr), &sp804_timer_ops); \
A Dpl061_gpio.h12 void pl061_gpio_register(uintptr_t base_addr, int gpio_dev);
/trusted-firmware-a/plat/arm/board/arm_fpga/
A Dfpga_console.c21 uintptr_t base_addr = PLAT_FPGA_CRASH_UART_BASE; in fpga_console_init() local
31 fdt_get_reg_props_by_index(fdt, node, 0, &base_addr, NULL); in fpga_console_init()
34 (void)console_pl011_register(base_addr, 0, 0, &console); in fpga_console_init()
/trusted-firmware-a/drivers/arm/sp804/
A Dsp804_delay_timer.c41 void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops) in sp804_timer_ops_init() argument
43 assert(base_addr != 0); in sp804_timer_ops_init()
46 sp804_base_addr = base_addr; in sp804_timer_ops_init()
/trusted-firmware-a/drivers/imx/timer/
A Dimx_gpt.c41 void imx_gpt_ops_init(uintptr_t base_addr) in imx_gpt_ops_init() argument
45 assert(base_addr != 0); in imx_gpt_ops_init()
47 imx_base_addr = base_addr; in imx_gpt_ops_init()
/trusted-firmware-a/drivers/marvell/mc_trustzone/
A Dmc_trustzone.c35 uint32_t val, base = win->base_addr; in tz_enable_win()
56 win->base_addr, base); in tz_enable_win()
71 (win->base_addr >> 32)); in tz_enable_win()
/trusted-firmware-a/plat/marvell/armada/a3k/common/
A Ddram_win.c48 uint64_t base_addr; member
205 win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> in dram_win_map_build()
207 win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT; in dram_win_map_build()
237 base_reg = (uint32_t)(win_cfg->base_addr / in cpu_win_set()
A Dio_addr_dec.c36 static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, in set_io_addr_dec_win() argument
51 base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << in set_io_addr_dec_win()
109 set_io_addr_dec_win(id, win->base_addr, win->win_size, dec_win); in set_io_addr_dec()
156 index, dram_wins_map->dram_windows[index].base_addr, in init_io_addr_dec()
/trusted-firmware-a/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.c17 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, in dfd_setup() argument
66 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); in dfd_setup()
85 dfd_base_addr = base_addr; in dfd_setup()
/trusted-firmware-a/plat/imx/imx8m/
A Dimx8m_psci_common.c42 uint64_t base_addr = BL31_BASE; in imx_pwr_domain_on() local
46 imx_set_cpu_secure_entry(core_id, base_addr); in imx_pwr_domain_on()
104 uint64_t base_addr = BL31_BASE; in imx_domain_suspend() local
110 imx_set_cpu_secure_entry(core_id, base_addr); in imx_domain_suspend()
/trusted-firmware-a/plat/mediatek/mt8195/drivers/dfd/
A Dplat_dfd.c17 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, in dfd_setup() argument
89 mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); in dfd_setup()
94 dfd_base_addr = base_addr; in dfd_setup()
/trusted-firmware-a/include/lib/extensions/
A Dras.h52 .memmap.base_addr = _base_addr, \
137 uintptr_t base_addr; member
183 return ser_probe_memmap(info->memmap.base_addr, info->memmap.size_num_k, in ras_err_ser_probe_memmap()
/trusted-firmware-a/bl1/
A Dbl1_fwu.c373 uintptr_t base_addr; in bl1_fwu_image_auth() local
409 base_addr = desc->image_info.image_base; in bl1_fwu_image_auth()
434 base_addr = image_src; in bl1_fwu_image_auth()
445 result = auth_mod_verify_img(image_id, (void *)base_addr, total_size); in bl1_fwu_image_auth()
457 zero_normalmem((void *)base_addr, total_size); in bl1_fwu_image_auth()
458 flush_dcache_range(base_addr, total_size); in bl1_fwu_image_auth()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dimx8mq_psci.c44 uint64_t base_addr = BL31_BASE; in imx_domain_suspend() local
51 imx_set_cpu_secure_entry(core_id, base_addr); in imx_domain_suspend()

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