| /trusted-firmware-a/lib/zlib/ |
| A D | inffast.c | 95 bits = state->bits;
104 if (bits < 15) {
106 bits += 8;
108 bits += 8;
114 bits -= op;
137 bits += 8;
139 bits += 8;
145 bits -= op;
293 len = bits >> 3;
295 bits -= len << 3;
[all …]
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| A D | inflate.c | 249 int bits;
261 if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR;
264 state->bits += (uInt)bits;
483 bits = state->bits; \
494 state->bits = bits; \
537 bits -= bits & 7; \
1056 if ((unsigned)(here.bits) <= bits) break;
1064 if ((unsigned)(last.bits + here.bits) <= bits) break;
1106 if ((unsigned)(here.bits) <= bits) break;
1114 if ((unsigned)(last.bits + here.bits) <= bits) break;
[all …]
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| A D | inftrees.c | 32 int ZLIB_INTERNAL inflate_table(type, lens, codes, table, bits, work) in inflate_table() argument
37 unsigned FAR *bits;
113 root = *bits;
119 here.bits = (unsigned char)1;
123 *bits = 1;
216 here.bits = (unsigned char)(len - drop);
285 (*table)[low].bits = (unsigned char)root;
295 here.bits = (unsigned char)(len - drop);
302 *bits = root;
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| A D | inftrees.h | 26 unsigned char bits; /* bits in this part of the code */ member
62 unsigned FAR *bits, unsigned short FAR *work));
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| A D | inflate.h | 102 unsigned bits; /* number of bits in "in" */ member
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| /trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/include/ |
| A D | t194_nvg.h | 156 } bits; member
165 } bits; member
176 } bits; member
185 } bits; member
196 } bits; member
206 } bits; member
214 } bits; member
245 } bits; member
253 } bits; member
263 } bits; member
[all …]
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| /trusted-firmware-a/include/drivers/brcm/ |
| A D | chimp.h | 48 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
49 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
68 static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
71 static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
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| /trusted-firmware-a/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.h | 89 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
90 (((bits) & (msk)) << (bits_shift))
91 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
93 REG_SET_BITS(bits, bits_shift, msk))
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| /trusted-firmware-a/plat/rockchip/common/include/ |
| A D | plat_private.h | 52 #define BITS_SHIFT(bits, shift) (bits << (shift)) argument
56 #define BITS_WITH_WMASK(bits, msk, shift)\ argument
57 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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| /trusted-firmware-a/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.h | 125 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
126 (((bits) & (msk)) << (bits_shift))
127 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
129 REG_SET_BITS(bits, bits_shift, msk))
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| /trusted-firmware-a/include/bl31/ |
| A D | ehf.h | 34 #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ argument
38 .pri_bits = (bits), \
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-2.rst | 41 A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
|
| A D | security-advisory-tfv-3.rst | 56 The vulnerability is due to incorrect handling of the execute-never bits in the
59 handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
68 of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
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| /trusted-firmware-a/drivers/brcm/ |
| A D | chimp.c | 49 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
52 mmio_clrbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_clrbits()
55 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
58 mmio_setbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_setbits()
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-2.rst.txt | 41 A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
|
| A D | security-advisory-tfv-3.rst.txt | 56 The vulnerability is due to incorrect handling of the execute-never bits in the
59 handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
68 of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
|
| /trusted-firmware-a/plat/rockchip/px30/ |
| A D | px30_def.h | 16 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) argument
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| /trusted-firmware-a/drivers/nxp/ddr/fsl-mmdc/ |
| A D | fsl_mmdc.c | 24 unsigned int bits) in set_wait_for_bits_clear() argument
30 while ((ddr_in32(ptr) & bits) != 0) { in set_wait_for_bits_clear()
|
| /trusted-firmware-a/fdts/ |
| A D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 9 * DDR width: 16bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
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| A D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 9 * DDR width: 32bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/components/ |
| A D | exception-handling.rst.txt | 23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
183 - Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
188 to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n`
189 distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits
197 upper bits of the 8 bits are writeable. In the scheme described above, when
198 choosing *n* bits for priority range assignment, the platform must ensure
199 that at least ``n+1`` top bits of GIC priority are writeable.
302 * This platform uses 2 bits for interrupt association. In total, 3 upper
303 * bits are in use.
[all …]
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| /trusted-firmware-a/docs/components/ |
| A D | exception-handling.rst | 23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
183 - Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
188 to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n`
189 distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits
197 upper bits of the 8 bits are writeable. In the scheme described above, when
198 choosing *n* bits for priority range assignment, the platform must ensure
199 that at least ``n+1`` top bits of GIC priority are writeable.
302 * This platform uses 2 bits for interrupt association. In total, 3 upper
303 * bits are in use.
[all …]
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| /trusted-firmware-a/plat/allwinner/common/ |
| A D | arisc_off.S | 20 # r3, so to be patched in the lower 16 bits of the first instruction,
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/ |
| A D | allwinner.rst.txt | 54 BL31 to only 28 bits of virtual address space, which reduces the number
88 SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
|
| /trusted-firmware-a/docs/plat/ |
| A D | allwinner.rst | 54 BL31 to only 28 bits of virtual address space, which reduces the number
88 SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
|