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Searched refs:cfg (Results 1 – 25 of 49) sorted by relevance

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/trusted-firmware-a/plat/brcm/board/stingray/include/
A Dscp_utils.h20 #define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \ argument
21 offsetof(M0CFG, cfg))
22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
23 offsetof(M0CFG, cfg), value)
25 #define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \ argument
26 offsetof(M0CFG, cfg))
28 offsetof(M0CFG, cfg), value)
30 #define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \ argument
31 offsetof(M0CFG, cfg))
32 #define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \ argument
[all …]
/trusted-firmware-a/drivers/amlogic/crypto/
A Dsha_dma.c19 uint32_t cfg; member
30 (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
32 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF))
37 (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
39 (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF))
44 (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF))
51 (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF))
58 (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF))
72 (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF))
79 (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF))
[all …]
/trusted-firmware-a/drivers/brcm/emmc/
A Demmc_pboot_hal_memory_drv.c134 p_sdhandle->device->cfg.blockSize)) { in bcm_emmc_init()
480 p_sdhandle->device->cfg.blockSize; in sdio_write()
510 p_sdhandle->device->cfg.blockSize)) { in sdio_write()
513 (p_sdhandle->device->cfg.blockSize - in sdio_write()
520 (p_sdhandle->device->cfg.blockSize - in sdio_write()
523 (p_sdhandle->device->cfg.blockSize - in sdio_write()
526 p_sdhandle->device->cfg.blockSize - in sdio_write()
537 p_sdhandle->device->cfg.blockSize; in sdio_write()
552 p_sdhandle->device->cfg.blockSize; in sdio_write()
559 p_sdhandle->device->cfg.blockSize); in sdio_write()
[all …]
A Demmc_chal_sd.c275 handle->cfg.voltage = 0; in chal_sd_init()
369 handle->cfg.dma = SD_DMA_OFF; in chal_sd_start()
381 handle->cfg.mode = mode; in chal_sd_start()
481 handle->cfg.dma = mode; in chal_sd_set_dma()
485 val |= handle->cfg.dma - 1; in chal_sd_set_dma()
491 handle->cfg.dma = 0; in chal_sd_set_dma()
509 if (handle->cfg.dma == SD_DMA_OFF) in chal_sd_get_dma_addr()
705 handle->cfg.dmaBoundary; in chal_sd_setup_xfer()
962 handle->cfg.speedMode = speed; in chal_sd_config()
963 handle->cfg.retryLimit = retry; in chal_sd_config()
[all …]
A Demmc_csl_sdcmd.c293 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd16()
295 handle->device->cfg.retryLimit); in sd_cmd16()
334 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd17()
336 handle->device->cfg.retryLimit); in sd_cmd17()
388 if (ntry > handle->device->cfg.retryLimit) { in sd_cmd18()
390 handle->device->cfg.retryLimit); in sd_cmd18()
444 handle->device->cfg.retryLimit); in card_sts_resp()
561 handle->device->cfg.retryLimit); in sd_cmd24()
615 handle->device->cfg.retryLimit); in sd_cmd25()
672 handle->device->cfg.wfe_retry); in mmc_cmd6()
[all …]
A Demmc_csl_sdcard.c211 handle->device->cfg.wfe_retry); in abort_err()
268 handle->device->cfg.wfe_retry); in process_data_xfer()
297 handle->device->cfg.wfe_retry); in process_data_xfer()
479 handle->device->cfg.blockSize = 512; in init_mmc_card()
658 blockSize = handle->device->cfg.blockSize; in write_buffer()
669 handle->device->cfg.wfe_retry); in write_buffer()
697 handle->device->cfg.wfe_retry); in write_buffer()
722 blockSize = handle->device->cfg.blockSize; in read_buffer()
732 handle->device->cfg.wfe_retry); in read_buffer()
761 handle->device->cfg.wfe_retry); in read_buffer()
[all …]
/trusted-firmware-a/plat/brcm/board/stingray/src/
A Diommu.c284 struct arm_smmu_cfg cfg[NUM_OF_SMRS]; member
308 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_smr_cfg()
321 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_s2cr_cfg()
446 smmu->cfg[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
461 reg = smmu->cfg[idx].cbar; in arm_smmu_create_identity_map()
466 ARM_SMMU_GR1_CBAR(smmu->cfg[idx].cbndx)), in arm_smmu_create_identity_map()
485 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
489 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
493 asid = smmu->cfg[idx].cbndx; in arm_smmu_create_identity_map()
498 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) + in arm_smmu_create_identity_map()
[all …]
/trusted-firmware-a/drivers/st/bsec/
A Dbsec.c180 uint32_t bsec_set_config(struct bsec_config *cfg) in bsec_set_config() argument
185 value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) & in bsec_set_config()
189 (((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) & in bsec_set_config()
198 result = bsec_power_safmem((bool)cfg->power & in bsec_set_config()
206 (((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) & in bsec_set_config()
208 (((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) & in bsec_set_config()
225 uint32_t bsec_get_config(struct bsec_config *cfg) in bsec_get_config() argument
229 if (cfg == NULL) { in bsec_get_config()
236 cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >> in bsec_get_config()
240 cfg->tread = (uint8_t)((value & BSEC_CONF_TREAD_MASK) >> in bsec_get_config()
[all …]
/trusted-firmware-a/plat/marvell/armada/a8k/a80x0/board/
A Dmarvell_plat_config.c168 .cfg.gpio.pin_count = 1,
169 .cfg.gpio.info = {{0, 35} },
170 .cfg.gpio.step_count = 7,
171 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
172 .cfg.gpio.delay_ms = 10,
/trusted-firmware-a/plat/marvell/armada/a8k/common/
A Dplat_pm.c510 assert((pm_cfg->cfg.gpio.pin_count < PMIC_GPIO_MAX_NUMBER) && in plat_marvell_power_off_gpio()
514 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
515 info = &pm_cfg->cfg.gpio.info[gpio]; in plat_marvell_power_off_gpio()
532 mdelay(pm_cfg->cfg.gpio.delay_ms); in plat_marvell_power_off_gpio()
537 for (idx = 0; idx < pm_cfg->cfg.gpio.step_count; idx++) { in plat_marvell_power_off_gpio()
538 tog_bits = pm_cfg->cfg.gpio.seq[idx]; in plat_marvell_power_off_gpio()
543 info = &pm_cfg->cfg.gpio.info[0]; in plat_marvell_power_off_gpio()
548 for (gpio = 0; gpio < pm_cfg->cfg.gpio.pin_count; gpio++) { in plat_marvell_power_off_gpio()
549 shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; in plat_marvell_power_off_gpio()
559 if (idx < pm_cfg->cfg.gpio.step_count - 1) { in plat_marvell_power_off_gpio()
[all …]
/trusted-firmware-a/include/common/
A Dinterrupt_props.h13 #define INTR_PROP_DESC(num, pri, grp, cfg) \ argument
18 .intr_cfg = (cfg), \
/trusted-firmware-a/include/drivers/marvell/
A Dthermal.h22 int (*ptr_tsen_probe)(struct tsen_config *cfg);
23 int (*ptr_tsen_read)(struct tsen_config *cfg, int *temp);
/trusted-firmware-a/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_cpu_pm_cpc.c162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config() argument
167 switch (cfg) { in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config() argument
209 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_cpu_pm_cpc.c162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config() argument
167 switch (cfg) { in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config() argument
209 switch (cfg) { in mtk_cpc_read_config()
/trusted-firmware-a/drivers/mtd/nand/
A Dspi_nand.c67 uint8_t cfg = spinand_dev.cfg_cache; in spi_nand_update_cfg() local
69 cfg &= ~mask; in spi_nand_update_cfg()
70 cfg |= val; in spi_nand_update_cfg()
72 if (cfg == spinand_dev.cfg_cache) { in spi_nand_update_cfg()
76 ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg); in spi_nand_update_cfg()
78 spinand_dev.cfg_cache = cfg; in spi_nand_update_cfg()
/trusted-firmware-a/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c202 uint32_t cfg; in tegra_soc_pwr_domain_suspend() local
234 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_suspend()
235 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { in tegra_soc_pwr_domain_suspend()
436 uint32_t cfg; in tegra_soc_pwr_domain_on_finish() local
513 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_on_finish()
514 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { in tegra_soc_pwr_domain_on_finish()
/trusted-firmware-a/drivers/arm/gic/v3/
A Dgicrv3_helpers.c130 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicr_set_icfgr() argument
138 (cfg & GIC_CFG_MASK) << bit_shift); in gicr_set_icfgr()
/trusted-firmware-a/fdts/
A Dstm32mp15xx-osd32.dtsi255 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
263 cfg = <2 65 1 0 0 PQR(1,1,1)>;
271 cfg = <1 33 1 16 36 PQR(1,1,1)>;
279 cfg = <3 98 5 7 7 PQR(1,1,1)>;
A Dstm32mp157a-avenger96.dts246 cfg = <2 80 0 0 0 PQR(1,0,0)>;
254 cfg = <2 65 1 0 0 PQR(1,1,1)>;
262 cfg = <1 33 1 16 36 PQR(1,1,1)>;
270 cfg = <1 39 3 11 4 PQR(1,1,1)>;
A Dstm32mp157c-odyssey-som.dtsi277 cfg = <2 80 0 0 0 PQR(1,0,0)>;
285 cfg = <2 65 1 0 0 PQR(1,1,1)>;
293 cfg = <1 33 1 16 36 PQR(1,1,1)>;
301 cfg = <3 98 5 7 7 PQR(1,1,1)>;
A Dstm32mp15xx-dkx.dtsi263 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
271 cfg = <2 65 1 0 0 PQR(1,1,1)>;
279 cfg = <1 33 1 16 36 PQR(1,1,1)>;
287 cfg = <3 98 5 7 7 PQR(1,1,1)>;
A Dstm32mp157c-ed1.dts273 cfg = <2 80 0 0 0 PQR(1,0,0)>;
281 cfg = <2 65 1 0 0 PQR(1,1,1)>;
289 cfg = <1 33 1 16 36 PQR(1,1,1)>;
297 cfg = <3 98 5 7 7 PQR(1,1,1)>;
/trusted-firmware-a/plat/marvell/armada/a8k/a70x0/
A Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
/trusted-firmware-a/plat/marvell/armada/a8k/a70x0_amc/
A Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
/trusted-firmware-a/plat/marvell/armada/a8k/a80x0_mcbin/
A Dplatform.mk13 DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg

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